diff options
| -rw-r--r-- | src/config/Config.lb | 30 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/Config.lb | 4 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/chip.h | 4 | ||||
| -rwxr-xr-x[-rw-r--r--] | src/cpu/ppc/ppc4xx/pci_bridge.c (renamed from src/mainboard/embeddedplanet/ep405pc/pci_bridge.c) | 4 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/pci_domain.c | 74 | ||||
| -rw-r--r-- | src/lib/Config.lb | 4 | ||||
| -rw-r--r-- | src/mainboard/embeddedplanet/ep405pc/Config.lb | 19 | ||||
| -rw-r--r-- | src/mainboard/embeddedplanet/ep405pc/Options.lb | 4 | ||||
| -rw-r--r-- | targets/embeddedplanet/ep405pc/Config.lb | 145 |
9 files changed, 170 insertions, 118 deletions
diff --git a/src/config/Config.lb b/src/config/Config.lb index 6a4b284f9d..4b446c3fe7 100644 --- a/src/config/Config.lb +++ b/src/config/Config.lb @@ -64,20 +64,20 @@ makerule linuxbios_ram.rom action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom" end -if CONFIG_USE_INIT -makerule init.o - depends "$(INIT-OBJECTS)" - action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)" - action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o" -end - -makerule linuxbios - depends "crt0.o init.o linuxbios_ram.rom ldscript.ld" - action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o" - action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" -end - -else +#if CONFIG_USE_INIT +#makerule init.o + #depends "$(INIT-OBJECTS)" + #action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)" + #action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o" +#end +# +#makerule linuxbios +# depends "crt0.o init.o linuxbios_ram.rom ldscript.ld" +# action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o" +# action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" +#end +# +#else makerule linuxbios depends "crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld" @@ -85,7 +85,7 @@ makerule linuxbios action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" end -end +#end makerule linuxbios.a depends "$(OBJECTS)" diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb index 353c25df2c..4bf4638762 100644 --- a/src/cpu/ppc/ppc4xx/Config.lb +++ b/src/cpu/ppc/ppc4xx/Config.lb @@ -20,8 +20,10 @@ initobject cache.S initobject sdram.c initobject clock.c -object mem.o +config chip.h object clock.o object cache.S +object pci_domain.o +driver pci_bridge.o dir /cpu/simple_init diff --git a/src/cpu/ppc/ppc4xx/chip.h b/src/cpu/ppc/ppc4xx/chip.h new file mode 100644 index 0000000000..0171a4f9ef --- /dev/null +++ b/src/cpu/ppc/ppc4xx/chip.h @@ -0,0 +1,4 @@ +struct cpu_ppc_ppc4xx_config +{ +}; +extern struct chip_operations cpu_ppc_ppc4xx_ops; diff --git a/src/mainboard/embeddedplanet/ep405pc/pci_bridge.c b/src/cpu/ppc/ppc4xx/pci_bridge.c index 4e67938105..26f608d144 100644..100755 --- a/src/mainboard/embeddedplanet/ep405pc/pci_bridge.c +++ b/src/cpu/ppc/ppc4xx/pci_bridge.c @@ -8,7 +8,7 @@ #include <console/console.h> static void -pci_bridge_init(struct device *dev) +pci_bridge_enable(struct device *dev) { printk_info("Configure PCI Bridge\n"); @@ -22,7 +22,7 @@ struct device_operations pci_bridge_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = pci_bridge_init, + .enable = pci_bridge_enable, .scan_bus = 0, }; diff --git a/src/cpu/ppc/ppc4xx/pci_domain.c b/src/cpu/ppc/ppc4xx/pci_domain.c new file mode 100644 index 0000000000..f53446dc88 --- /dev/null +++ b/src/cpu/ppc/ppc4xx/pci_domain.c @@ -0,0 +1,74 @@ +/* + * Initialisation of the PCI bridge . + */ + +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> + +static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +{ + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; +} + +static void pci_domain_read_resources(device_t dev) +{ + struct resource *resource; + + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); + resource->limit = 0xffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void pci_domain_set_resources(device_t dev) +{ + int idx = 3; /* who knows? */ + + ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10); + assign_resources(&dev->link[0]); +} + +struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = &pci_ppc_conf1 +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } +} + +struct chip_operations cpu_ppc_ppc4xx_ops = { + CHIP_NAME("PPC 4XX CPU") + .enable_dev = enable_dev, +}; diff --git a/src/lib/Config.lb b/src/lib/Config.lb index 3a1baf66c3..e6234d4c42 100644 --- a/src/lib/Config.lb +++ b/src/lib/Config.lb @@ -17,7 +17,7 @@ makedefine .PHONY : version.o if CONFIG_USE_INIT initobject uart8250.c -# initobject memset.o + initobject memset.o initobject memcpy.o -# initobject memcmp.o + initobject memcmp.o end diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb index 9f071bf621..a47d1c6487 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Config.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb @@ -6,16 +6,19 @@ ## Early board initialization, called from ppc_main() ## initobject init.c -driver pci_bridge.c arch ppc end -chip cpu/ppc/ppc4xx device pnp 0.0 on end end - -## -## Include the secondary Configuration files -## -chip southbridge/winbond/w83c553 device pnp 0.0 on end end - +chip cpu/ppc/ppc4xx + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/winbond/w83c553 + device pci 9.0 on end # ISA bridge + device pci 9.1 on end # IDE contoller + end + device pci e.0 on end + end +end + ## ## Build the objects we have code for in this directory. ## diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb index d37db77dc2..3275aa297d 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Options.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb @@ -69,8 +69,8 @@ default _IO_BASE=ISA_IO_BASE default TTYS0_BASE=0xef600300-ISA_IO_BASE ## Enable PPC405 instructions -default CPU_OPT="-Wa,-m405" -default CPU_OPT="" +default CPU_OPT="-mcpu=405" +#default CPU_OPT="" ## Use stage 1 initialization code default CONFIG_USE_INIT=1 diff --git a/targets/embeddedplanet/ep405pc/Config.lb b/targets/embeddedplanet/ep405pc/Config.lb index d9c03ff11e..8862a8566b 100644 --- a/targets/embeddedplanet/ep405pc/Config.lb +++ b/targets/embeddedplanet/ep405pc/Config.lb @@ -1,96 +1,66 @@ # Config file for Embedded Planet EP405PC board # This will make a target directory of ./ep405pc -loadoptions - target ep405pc - -uses CPU_OPT -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE -uses CONFIG_COMPRESS -uses CONFIG_CHIP_CONFIGURE -uses DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_USE_INIT -uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD TTYS0_DIV -uses NO_POST -uses CONFIG_IDE -uses CONFIG_FS_STREAM -uses CONFIG_FS_EXT2 -uses CONFIG_FS_ISO9660 -uses CONFIG_FS_FAT -uses AUTOBOOT_CMDLINE -uses CONFIG_SYS_CLK_FREQ -uses IDE_BOOT_DRIVE -uses IDE_SWAB IDE_OFFSET -uses ROM_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses EMBEDDED_RAM_SIZE -uses STACK_SIZE HEAP_SIZE - -## Enable PPC405 instructions -option CPU_OPT="-Wa,-m405" - -## use a cross compiler -#option CROSS_COMPILE="powerpc-eabi-" - -## Use stage 1 initialization code -option CONFIG_USE_INIT=1 - -## Use chip configuration -option CONFIG_CHIP_CONFIGURE=1 - -## We don't use compressed image -option CONFIG_COMPRESS=0 - -## Turn off POST codes -option NO_POST=1 - -## Enable serial console -option DEFAULT_CONSOLE_LOGLEVEL=8 -option CONFIG_CONSOLE_SERIAL8250=1 -# Divisor of 69 == 9600 baud due to weird clocking -option TTYS0_DIV=69 -option TTYS0_BAUD=9600 - -## Boot linux from IDE -option CONFIG_IDE=1 -option CONFIG_FS_STREAM=1 -option CONFIG_FS_EXT2=1 -option CONFIG_FS_ISO9660=1 -option CONFIG_FS_FAT=1 -option AUTOBOOT_CMDLINE="hda1:/vmlinuz" - -option ROM_SIZE=1048576 - -## Board has fixed size RAM -option EMBEDDED_RAM_SIZE=64*1024*1024 - -## LinuxBIOS C code runs at this location in RAM -option _RAMBASE=0x00100000 - -## -## Use a 64K stack -## -option STACK_SIZE=0x10000 - -## -## Use a 64K heap -## -option HEAP_SIZE=0x10000 - -## -## System clock -## -option CONFIG_SYS_CLK_FREQ=33 +mainboard embeddedplanet/ep405pc romimage "normal" + ## Enable PPC405 instructions + option CPU_OPT="-mcpu=405" + + ## use a cross compiler + #option CROSS_COMPILE="powerpc-ibm-eabi-" + + ## Use stage 1 initialization code + option CONFIG_USE_INIT=1 + + ## Use chip configuration + option CONFIG_CHIP_CONFIGURE=1 + + ## We don't use compressed image + option CONFIG_COMPRESS=0 + + ## Turn off POST codes + option NO_POST=1 + + ## Enable serial console + option DEFAULT_CONSOLE_LOGLEVEL=8 + option CONFIG_CONSOLE_SERIAL8250=1 + # Divisor of 69 == 9600 baud due to weird clocking + option TTYS0_DIV=69 + option TTYS0_BAUD=9600 + + ## Boot linux from IDE + option CONFIG_IDE=1 + option CONFIG_FS_STREAM=1 + option CONFIG_FS_EXT2=1 + option CONFIG_FS_ISO9660=1 + option CONFIG_FS_FAT=1 + option AUTOBOOT_CMDLINE="hda1:/vmlinuz" + + option ROM_SIZE=1048576 + + ## Board has fixed size RAM + option EMBEDDED_RAM_SIZE=64*1024*1024 + + ## LinuxBIOS C code runs at this location in RAM + option _RAMBASE=0x00100000 + + ## + ## Use a 64K stack + ## + option STACK_SIZE=0x10000 + + ## + ## Use a 64K heap + ## + option HEAP_SIZE=0x10000 + + ## + ## System clock + ## + option CONFIG_SYS_CLK_FREQ=33 + ## option _ROMBASE=0xfff00000 @@ -106,7 +76,6 @@ romimage "normal" ## linuxBIOS C code runs at this location in RAM option _RAMBASE=0x00100000 - mainboard embeddedplanet/ep405pc end buildrom ./linuxbios.rom ROM_SIZE "normal" |