diff options
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/p2sb.h | 25 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 25 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/p2sb.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/p2sb.c | 43 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/smihandler.c | 32 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/p2sb.h | 32 | ||||
| -rw-r--r-- | src/soc/intel/common/block/p2sb/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 113 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 25 | ||||
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 46 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/p2sb.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/p2sb.c | 46 |
16 files changed, 276 insertions, 134 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ead6bf3f03..f9c62282ff 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/systemagent.h> @@ -54,12 +55,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) bootblock_systemagent_early_init(); - dev = PCH_DEV_P2SB; - /* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + p2sb_enable_bar(); + p2sb_configure_hpet(); /* Decode the ACPI I/O port range for early firmware verification.*/ dev = PCH_DEV_PMC; diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h new file mode 100644 index 0000000000..01ba7ffd24 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/p2sb.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_P2SB_H_ +#define _SOC_P2SB_H_ + +/* PCI config space registers */ +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0xB0 + +#endif /* _SOC_P2SB_H_ */ diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 86f147d0c3..f8f91980bb 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,6 +19,7 @@ bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c bootblock-y += lpc.c +bootblock-y += p2sb.c bootblock-$(CONFIG_UART_DEBUG) += uart.c romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c @@ -45,6 +46,7 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += nhlt.c +ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -56,6 +58,7 @@ ramstage-y += vr_config.c ramstage-y += sd.c smm-y += gpio.c +smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index dc70a4f6c7..eb67012781 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -18,9 +18,10 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> -#include <intelblocks/rtc.h> #include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> #include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> @@ -50,25 +51,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -static void enable_p2sbbar(void) -{ - pci_devfn_t dev = PCH_DEV_P2SB; - - /* Enable PCR Base address in PCH */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - - /* Enable P2SB MSE */ - pci_write_config8(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* - * Enable decoding for HPET memory address range. - * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode - * the High Performance Timer memory address range - * selected by bits 1:0 - */ - pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); -} - static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -96,7 +78,8 @@ void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); gspi_early_bar_init(); - enable_p2sbbar(); + p2sb_enable_bar(); + p2sb_configure_hpet(); /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/cannonlake/include/soc/p2sb.h b/src/soc/intel/cannonlake/include/soc/p2sb.h index 8b2e437f87..73a50537a3 100644 --- a/src/soc/intel/cannonlake/include/soc/p2sb.h +++ b/src/soc/intel/cannonlake/include/soc/p2sb.h @@ -20,8 +20,5 @@ #define HPTC_ADDR_ENABLE_BIT (1 << 7) #define PCH_P2SB_EPMASK0 0x220 -#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) - -#define PCH_P2SB_E0 0xE0 #endif diff --git a/src/soc/intel/cannonlake/p2sb.c b/src/soc/intel/cannonlake/p2sb.c new file mode 100644 index 0000000000..6a7fac4963 --- /dev/null +++ b/src/soc/intel/cannonlake/p2sb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <intelblocks/p2sb.h> + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = (1 << 31) | (1 << 30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 0ecc66df02..5f9e0f82af 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> #include <soc/p2sb.h> @@ -35,33 +36,8 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) return &em64t101_smm_ops; } -static void pch_configure_endpoints(pci_devfn_t dev, int epmask_id, - uint32_t mask) -{ - uint32_t reg32; - - reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); -} - -static void disable_sideband_access(pci_devfn_t dev) -{ - u8 reg8; - uint32_t mask; - - /* Remove the host accessing right to PSF register range. */ - /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); - pch_configure_endpoints(dev, 5, mask); - - /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); - pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); -} - static void pch_disable_heci(void) { - pci_devfn_t dev = PCH_DEV_P2SB; struct pcr_sbi_msg msg = { .pid = PID_CSME0, .offset = 0, @@ -77,7 +53,7 @@ static void pch_disable_heci(void) int status; /* unhide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); + p2sb_unhide(); /* Send SBI command to make HECI#1 function disable */ status = pcr_execute_sideband_msg(&msg, &data32, &response); @@ -85,10 +61,10 @@ static void pch_disable_heci(void) printk(BIOS_ERR, "Fail to make CSME function disable\n"); /* Ensure to Lock SBI interface after this command */ - disable_sideband_access(dev); + p2sb_disable_sideband_access(); /* hide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); + p2sb_hide(); } /* diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 8139a69b62..e5c1f3ef6a 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,37 @@ #ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H #define SOC_INTEL_COMMON_BLOCK_P2SB_H +#include <stddef.h> +#include <stdint.h> + +#define PCH_P2SB_E0 0xe0 +#define P2SB_E0_MASKLOCK (1 << 1) + +enum { + P2SB_EP_MASK_0_REG, + P2SB_EP_MASK_1_REG, + P2SB_EP_MASK_2_REG, + P2SB_EP_MASK_3_REG, + P2SB_EP_MASK_4_REG, + P2SB_EP_MASK_5_REG, + P2SB_EP_MASK_6_REG, + P2SB_EP_MASK_7_REG, + P2SB_EP_MASK_MAX_REG, +}; + void p2sb_unhide(void); void p2sb_hide(void); +void p2sb_disable_sideband_access(void); +void p2sb_enable_bar(void); +void p2sb_configure_hpet(void); + +/* SOC overrides */ +/* + * Each SoC should implement EP Mask register to disable SB access + * Input: + * ep_mask: An array to be filled by SoC code with EP mask register. + * count: number of element in EP mask array. + */ +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count); #endif /* SOC_INTEL_COMMON_BLOCK_P2SB_H */ diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index d78714b03e..a1330abdd9 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1 +1,3 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 6a9bd34668..c09c6aa7ef 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright 2016 Google Inc. + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,38 +19,132 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/p2sb.h> #include <rules.h> #include <soc/iomap.h> +#include <soc/p2sb.h> #include <soc/pci_devs.h> -#include <intelblocks/p2sb.h> +#include <string.h> + +#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) -#define P2SB_E0 0xe0 #define HIDE_BIT (1 << 0) +#if defined(__SIMPLE_DEVICE__) +static pci_devfn_t p2sb_get_device(void) +{ + int devfn = PCH_DEVFN_P2SB; + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + if (dev == PCI_DEV_INVALID) + die("PCH_DEV_P2SB not found!\n"); + + return dev; +} +#else +static struct device *p2sb_get_device(void) +{ + struct device *dev = PCH_DEV_P2SB; + if (!dev) + die("PCH_DEV_P2SB not found!\n"); + + return dev; +} +#endif + +#define P2SB_GET_DEV p2sb_get_device() + +void p2sb_enable_bar(void) +{ + /* Enable PCR Base address in PCH */ + pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_0, P2SB_BAR); + pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_1, 0); + + /* Enable P2SB MSE */ + pci_write_config8(P2SB_GET_DEV, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + +/* + * Enable decoding for HPET range. + * This is needed for FspMemoryInit to store and retrieve a global data + * pointer. + */ +void p2sb_configure_hpet(void) +{ + /* + * Enable decoding for HPET memory address range. + * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode + * the High Performance Timer memory address range + * selected by bits 1:0 + */ + pci_write_config8(P2SB_GET_DEV, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); +} + static void p2sb_set_hide_bit(int hide) { - struct device *dev; - const uint16_t reg = P2SB_E0 + 1; + const uint16_t reg = PCH_P2SB_E0 + 1; const uint8_t mask = HIDE_BIT; uint8_t val; - dev = PCH_DEV_P2SB; - - val = pci_read_config8(dev, reg); + val = pci_read_config8(P2SB_GET_DEV, reg); val &= ~mask; if (hide) val |= mask; - pci_write_config8(dev, reg, val); + pci_write_config8(P2SB_GET_DEV, reg, val); } void p2sb_unhide(void) { p2sb_set_hide_bit(0); + + if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + PCI_VENDOR_ID_INTEL) + die("Unable to unhide PCH_DEV_P2SB device !\n"); } void p2sb_hide(void) { p2sb_set_hide_bit(1); + + if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + 0xFFFF) + die("Unable to hide PCH_DEV_P2SB device !\n"); +} + +static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) +{ + uint32_t reg32; + + reg32 = pci_read_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id)); + pci_write_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id), + reg32 | mask); +} + +static void p2sb_lock_endpoints(void) +{ + uint8_t reg8; + + /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ + reg8 = pci_read_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2); + pci_write_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2, + reg8 | P2SB_E0_MASKLOCK); +} + +void p2sb_disable_sideband_access(void) +{ + uint32_t ep_mask[P2SB_EP_MASK_MAX_REG]; + int i; + + memset(ep_mask, 0, sizeof(ep_mask)); + + p2sb_soc_get_sb_mask(ep_mask, ARRAY_SIZE(ep_mask)); + + /* Remove the host accessing right to PSF register range. */ + for (i = 0; i < P2SB_EP_MASK_MAX_REG; i++) + p2sb_configure_endpoints(i, ep_mask[i]); + + p2sb_lock_endpoints(); } static void read_resources(struct device *dev) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef95cf7767..89e48f1232 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -16,6 +16,7 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c bootblock-y += gspi.c +bootblock-y += p2sb.c bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += lpc.c @@ -54,6 +55,7 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c ramstage-y += memmap.c +ramstage-y += p2sb.c ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c @@ -68,6 +70,7 @@ ramstage-y += vr_config.c smm-y += elog.c smm-y += gpio.c +smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index cc8f43725b..2c3df09cc4 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -33,6 +33,7 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> #include <intelblocks/sgx.h> #include <intelblocks/uart.h> #include <intelblocks/systemagent.h> diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ef61a60291..4c88ed55bf 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -22,9 +22,10 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> -#include <intelblocks/rtc.h> #include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> #include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> @@ -44,29 +45,11 @@ #define PCR_DMI_PMBASEC 0x27B0 #define PCR_DMI_TCOBASE 0x2778 -static void enable_p2sbbar(void) -{ - pci_devfn_t dev = PCH_DEV_P2SB; - - /* Enable PCR Base address in PCH */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - - /* Enable P2SB MSE */ - pci_write_config8(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* - * Enable decoding for HPET memory address range. - * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode - * the High Performance Timer memory address range - * selected by bits 1:0 - */ - pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); -} - void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); - enable_p2sbbar(); + p2sb_enable_bar(); + p2sb_configure_hpet(); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index e640ceb40a..12dbab4814 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -40,40 +40,9 @@ #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) -static void pch_configure_endpoints(struct device *dev, int epmask_id, - uint32_t mask) +static void disable_sideband_access(void) { - uint32_t reg32; - - reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); -} - -static void disable_sideband_access(struct device *dev) -{ - u8 reg8; - uint32_t mask; - - /* - * Set p2sb PCI offset EPMASK5 C4h [29, 28, 27, 26] to disable Sideband - * access for PCI Root Bridge. - * Set p2sb PCI offset EPMASK5 C4h [17, 16,10, 1] to disable Sideband - * access for MIPI controller. - */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | - (1 << 16) | (1 << 10) | (1 << 1); - pch_configure_endpoints(dev, 5, mask); - - /* - * Set p2sb PCI offset EPMASK7 CCh ports E6, E5 (bits 6, 5) - * to disable Sideband access for XHCI controller. - */ - mask = (1 << 6) | (1 << 5); - pch_configure_endpoints(dev, 7, mask); - - /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); - pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); + p2sb_disable_sideband_access(); /* hide p2sb device */ p2sb_hide(); @@ -81,15 +50,6 @@ static void disable_sideband_access(struct device *dev) static void pch_disable_heci(void) { - struct device *dev = PCH_DEV_P2SB; - - /* - * if p2sb device 1f.1 is not present or hidden in devicetree - * p2sb device becomes NULL - */ - if (!dev) - return; - /* unhide p2sb device */ p2sb_unhide(); @@ -97,7 +57,7 @@ static void pch_disable_heci(void) pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); - disable_sideband_access(dev); + disable_sideband_access(); } static void pch_finalize_script(struct device *dev) diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index 09e73fc254..8d7c11af75 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -23,9 +23,7 @@ #define PCH_P2SB_HBDF 0x70 #define PCH_P2SB_EPMASK0 0xB0 -#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) -#define PCH_P2SB_E0 0xE0 #define PCH_PWRM_ACPI_TMR_CTL 0xFC #endif /* _SOC_P2SB_H_ */ diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c new file mode 100644 index 0000000000..c1e9118248 --- /dev/null +++ b/src/soc/intel/skylake/p2sb.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <intelblocks/p2sb.h> + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + * Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband + * access for MIPI controller. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | + (1 << 16) | (1 << 10) | (1 << 1); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband + * access for XHCI controller. + */ + mask = (1 << 6) | (1 << 5); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} |