diff options
| -rw-r--r-- | src/mainboard/intel/truxton/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/truxton/romstage.c | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 13 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.h | 1 |
4 files changed, 6 insertions, 20 deletions
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig index 5aa4b57cfd..11058e6097 100644 --- a/src/mainboard/intel/truxton/Kconfig +++ b/src/mainboard/intel/truxton/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I3100 select SUPERIO_INTEL_I3100 select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 960cccb8d6..0677cf6940 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -31,7 +31,6 @@ #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" #include "superio/intel/i3100/i3100.h" -#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/intel/i3100/early_serial.c" #include "lib/debug.c" // XXX @@ -47,16 +46,12 @@ static inline int spd_read_byte(u16 device, u8 address) #include "northbridge/intel/i3100/raminit_ep80579.c" #include "lib/generic_sdram.c" -#include "../../intel/jarrell/debug.c" -#include "arch/x86/lib/stages.c" #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) #include <cpu/intel/romstage.h> -static void main(unsigned long bist) +void main(unsigned long bist) { - msr_t msr; - u16 perf; static const struct mem_controller mch[] = { { .node_id = 0, @@ -67,9 +62,8 @@ static void main(unsigned long bist) if (bist == 0) { /* Skip this if there was a built in self test failure */ - early_mtrr_init(); if (memory_initialized()) - skip_romstage(); + return; } /* Set up the console */ @@ -89,7 +83,6 @@ static void main(unsigned long bist) print_pci_devices(); #endif enable_smbus(); - dump_spd_registers(); sdram_initialize(ARRAY_SIZE(mch), mch); dump_pci_devices(); diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 962b7aa86b..cff7879f5e 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <lib.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/intel/speedstep.h> @@ -37,7 +38,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, }; int i; - int max; for (i = 0; i < ARRAY_SIZE(register_values); i += 3) { device_t dev; @@ -61,7 +61,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, ddr2; + int value, low; sz.side1 = 0; sz.side2 = 0; @@ -489,7 +489,6 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, static void sdram_set_spd_registers(const struct mem_controller *ctrl) { u8 dimm_mask; - int i; /* Test if we can read the SPD */ dimm_mask = spd_detect_dimms(ctrl); @@ -503,9 +502,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { u8 c1,c2; - u32 dimm, i; + u32 i; u32 data32 = 0; - u32 t4; /* Set up northbridge values */ /* ODT enable */ @@ -565,8 +563,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) u32 drc; u32 data32; u32 mode_reg; - msr_t msr; - u16 data16; mask = spd_detect_dimms(ctrl); print_debug("Starting SDRAM Enable\n"); @@ -771,9 +767,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Set the ECC mode */ pci_write_config32(ctrl->f0, DRC, drc); - - /* The memory is now set up--use it */ - cache_ramstage(); } static inline int memory_initialized(void) diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h index 38c68454fc..e84736df6d 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.h +++ b/src/northbridge/intel/i3100/raminit_ep80579.h @@ -27,4 +27,5 @@ struct mem_controller { u16 channel0[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); #endif |