diff options
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/common/gpio.c | 153 | ||||
| -rw-r--r-- | src/southbridge/intel/common/gpio.h | 188 |
4 files changed, 346 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 949310bb58..7bc686defa 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -1,2 +1,4 @@ config SOUTHBRIDGE_INTEL_COMMON def_bool n +config SOUTHBRIDGE_INTEL_COMMON_GPIO + def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 513f2889c7..56ba56fc01 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -21,4 +21,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c endif diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c new file mode 100644 index 0000000000..aadd5198f0 --- /dev/null +++ b/src/southbridge/intel/common/gpio.c @@ -0,0 +1,153 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2016 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +#include "gpio.h" + +#define MAX_GPIO_NUMBER 75 /* zero based */ + +static u16 get_gpio_base(void) +{ +#if defined(__PRE_RAM__) || defined(__SMM__) + return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; +#else + return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + GPIO_BASE) & 0xfffc; +#endif +} + +void setup_pch_gpios(const struct pch_gpio_map *gpio) +{ + u16 gpiobase = get_gpio_base(); + + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} + +/* + * return current gpio level. + */ +int get_gpio(int gpio_num) +{ + static const int gpio_reg_offsets[] = {GP_LVL, GP_LVL2, GP_LVL3}; + u16 gpio_base = get_gpio_base(); + int index, bit; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; +} + +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + if (get_gpio(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} + +/* + * set gpio output to level. + */ +void set_gpio(int gpio_num, int value) +{ + static const int gpio_reg_offsets[] = { + GP_LVL, GP_LVL2, GP_LVL3 + }; + u16 gpio_base = get_gpio_base(); + int index, bit; + u32 config; + + if (gpio_num > MAX_GPIO_NUMBER) + return; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + config = inl(gpio_base + gpio_reg_offsets[index]); + config &= ~(1 << bit); + config |= value << bit; + outl(config, gpio_base + gpio_reg_offsets[index]); +} + +int gpio_is_native(int gpio_num) +{ + static const int gpio_reg_offsets[] = { + GPIO_USE_SEL, GPIO_USE_SEL2, GPIO_USE_SEL3 + }; + u16 gpio_base = get_gpio_base(); + int index, bit; + u32 config; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + config = inl(gpio_base + gpio_reg_offsets[index]); + return !(config & (1 << bit)); +} diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h new file mode 100644 index 0000000000..7b42b0680f --- /dev/null +++ b/src/southbridge/intel/common/gpio.h @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2016 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INTEL_COMMON_GPIO_H +#define INTEL_COMMON_GPIO_H + +#include <stdint.h> + +/* LPC GPIO Base Address Register */ +#define GPIO_BASE 0x48 +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) + +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_NO_INVERT 0 +#define GPIO_INVERT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_NO_BLINK 0 +#define GPIO_BLINK 1 + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_gpio_set1 { + u32 gpio0 : 1; + u32 gpio1 : 1; + u32 gpio2 : 1; + u32 gpio3 : 1; + u32 gpio4 : 1; + u32 gpio5 : 1; + u32 gpio6 : 1; + u32 gpio7 : 1; + u32 gpio8 : 1; + u32 gpio9 : 1; + u32 gpio10 : 1; + u32 gpio11 : 1; + u32 gpio12 : 1; + u32 gpio13 : 1; + u32 gpio14 : 1; + u32 gpio15 : 1; + u32 gpio16 : 1; + u32 gpio17 : 1; + u32 gpio18 : 1; + u32 gpio19 : 1; + u32 gpio20 : 1; + u32 gpio21 : 1; + u32 gpio22 : 1; + u32 gpio23 : 1; + u32 gpio24 : 1; + u32 gpio25 : 1; + u32 gpio26 : 1; + u32 gpio27 : 1; + u32 gpio28 : 1; + u32 gpio29 : 1; + u32 gpio30 : 1; + u32 gpio31 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_set2 { + u32 gpio32 : 1; + u32 gpio33 : 1; + u32 gpio34 : 1; + u32 gpio35 : 1; + u32 gpio36 : 1; + u32 gpio37 : 1; + u32 gpio38 : 1; + u32 gpio39 : 1; + u32 gpio40 : 1; + u32 gpio41 : 1; + u32 gpio42 : 1; + u32 gpio43 : 1; + u32 gpio44 : 1; + u32 gpio45 : 1; + u32 gpio46 : 1; + u32 gpio47 : 1; + u32 gpio48 : 1; + u32 gpio49 : 1; + u32 gpio50 : 1; + u32 gpio51 : 1; + u32 gpio52 : 1; + u32 gpio53 : 1; + u32 gpio54 : 1; + u32 gpio55 : 1; + u32 gpio56 : 1; + u32 gpio57 : 1; + u32 gpio58 : 1; + u32 gpio59 : 1; + u32 gpio60 : 1; + u32 gpio61 : 1; + u32 gpio62 : 1; + u32 gpio63 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_set3 { + u32 gpio64 : 1; + u32 gpio65 : 1; + u32 gpio66 : 1; + u32 gpio67 : 1; + u32 gpio68 : 1; + u32 gpio69 : 1; + u32 gpio70 : 1; + u32 gpio71 : 1; + u32 gpio72 : 1; + u32 gpio73 : 1; + u32 gpio74 : 1; + u32 gpio75 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_map { + struct { + const struct pch_gpio_set1 *mode; + const struct pch_gpio_set1 *direction; + const struct pch_gpio_set1 *level; + const struct pch_gpio_set1 *reset; + const struct pch_gpio_set1 *invert; + const struct pch_gpio_set1 *blink; + } set1; + struct { + const struct pch_gpio_set2 *mode; + const struct pch_gpio_set2 *direction; + const struct pch_gpio_set2 *level; + const struct pch_gpio_set2 *reset; + } set2; + struct { + const struct pch_gpio_set3 *mode; + const struct pch_gpio_set3 *direction; + const struct pch_gpio_set3 *level; + const struct pch_gpio_set3 *reset; + } set3; +}; + +extern const struct pch_gpio_map mainboard_gpio_map; + +/* Configure GPIOs with mainboard provided settings */ +void setup_pch_gpios(const struct pch_gpio_map *gpio); + +/* get GPIO pin value */ +int get_gpio(int gpio_num); +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); + +void set_gpio(int gpio_num, int value); + +void clear_gpio(int gpio_num); + +int gpio_is_native(int gpio_num); + +#endif |