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-rw-r--r--src/mainboard/intel/d510mo/Kconfig1
-rw-r--r--src/mainboard/intel/d510mo/romstage.c20
2 files changed, 16 insertions, 5 deletions
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
index 757a24cfd4..0f747cc878 100644
--- a/src/mainboard/intel/d510mo/Kconfig
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627THG
select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_INT15
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index f99e185f2a..1bf2b61018 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -103,6 +103,7 @@ void mainboard_romstage_entry(unsigned long bist)
const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
int cbmem_was_initted;
int s3resume = 0;
+ int boot_path;
if (bist == 0)
enable_lapic();
@@ -124,15 +125,24 @@ void mainboard_romstage_entry(unsigned long bist)
post_code(0x30);
+ s3resume = southbridge_detect_s3_resume();
+
+ if (s3resume) {
+ boot_path = BOOT_PATH_RESUME;
+ } else {
+ if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
+ boot_path = BOOT_PATH_RESET;
+ else
+ boot_path = BOOT_PATH_NORMAL;
+ }
+
printk(BIOS_DEBUG, "Initializing memory\n");
- if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
- sdram_initialize(BOOT_PATH_RESET, spd_addrmap);
- else
- sdram_initialize(BOOT_PATH_NORMAL, spd_addrmap);
+ sdram_initialize(boot_path, spd_addrmap);
printk(BIOS_DEBUG, "Memory initialized\n");
post_code(0x31);
- ram_check(0x200000,0x300000);
+
+ quick_ram_check();
rcba_config();