diff options
| -rw-r--r-- | src/cpu/amd/agesa/amd_late_init.c | 18 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family16kb/northbridge.c | 16 |
2 files changed, 16 insertions, 18 deletions
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index a0a3516835..26442f4913 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -19,10 +19,6 @@ #include <arch/acpi.h> #include <bootstate.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> @@ -38,20 +34,6 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB) - device_t dev; - u32 value; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); -#endif - #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 72967c129c..def29d1f87 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -653,9 +653,25 @@ static const struct pci_driver family10_northbridge __pci_driver = { .device = PCI_DEVICE_ID_AMD_10H_NB_HT, }; +static void fam16_finalize(void *chip_info) +{ + device_t dev; + u32 value; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); +} + struct chip_operations northbridge_amd_agesa_family16kb_ops = { CHIP_NAME("AMD FAM16 Northbridge") .enable_dev = 0, + .final = fam16_finalize, }; static void domain_read_resources(device_t dev) |