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-rw-r--r--src/southbridge/intel/i82801dx/Kconfig4
-rw-r--r--src/southbridge/intel/i82801dx/bootblock.c21
2 files changed, 25 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index af8300e8ed..82db1c3752 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -29,4 +29,8 @@ config EHCI_BAR
hex
default 0xfef00000
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/intel/i82801dx/bootblock.c"
+
endif
diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c
new file mode 100644
index 0000000000..8ae419dd9b
--- /dev/null
+++ b/src/southbridge/intel/i82801dx/bootblock.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+static void bootblock_southbridge_init(void)
+{
+ /* Set FWH IDs for 2 MB flash part. */
+ if (CONFIG_ROM_SIZE == 0x200000)
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);
+}