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-rw-r--r--src/soc/nvidia/tegra132/Makefile.inc1
-rw-r--r--src/soc/nvidia/tegra132/ccplex.c61
-rw-r--r--src/soc/nvidia/tegra132/ccplex.h28
-rw-r--r--src/soc/nvidia/tegra132/romstage.c7
4 files changed, 95 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index a98467431b..c14f1c8530 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -19,6 +19,7 @@ endif
romstage-y += cbfs.c
romstage-y += cbmem.c
romstage-y += timer.c
+romstage-y += ccplex.c
romstage-y += clock.c
romstage-y += spi.c
romstage-y += i2c.c
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
new file mode 100644
index 0000000000..b569bd2124
--- /dev/null
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <cbfs.h>
+#include <soc/addressmap.h>
+#include "ccplex.h"
+#include "mc.h"
+
+#define MTS_FILE_NAME "mts"
+
+int ccplex_load_mts(void)
+{
+ struct cbfs_file file;
+ ssize_t offset;
+ size_t nread;
+ /*
+ * MTS location is hard coded to this magic address. The hardware will
+ * take the MTS from this location and place it in the final resting
+ * place in the carveout region.
+ */
+ void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS;
+ struct cbfs_media *media = CBFS_DEFAULT_MEDIA;
+
+ offset = cbfs_locate_file(media, &file, MTS_FILE_NAME);
+ if (offset < 0) {
+ printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME);
+ return -1;
+ }
+
+ /* Read MTS file into the carveout region. */
+ nread = cbfs_read(media, mts, offset, file.len);
+
+ if (nread != file.len) {
+ printk(BIOS_DEBUG, "MTS bytes read (%zu) != file length(%u)!\n",
+ nread, file.len);
+ return -1;
+ }
+
+ printk(BIOS_DEBUG, "MTS: %zu bytes loaded @ %p\n", nread, mts);
+
+ return 0;
+}
diff --git a/src/soc/nvidia/tegra132/ccplex.h b/src/soc/nvidia/tegra132/ccplex.h
new file mode 100644
index 0000000000..6b9699cded
--- /dev/null
+++ b/src/soc/nvidia/tegra132/ccplex.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_CCPLEX_H__
+#define __SOC_NVIDIA_TEGRA132_CCPLEX_H__
+
+#define MTS_LOAD_ADDRESS 0x82000000
+
+/* Loads the MTS microcode. Return 0 on success, < 0 on error. */
+int ccplex_load_mts(void);
+
+#endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 20429a5e53..3bc2231131 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -23,7 +23,8 @@
#include <arch/exception.h>
#include <soc/sdram_configs.h>
-#include <soc/nvidia/tegra132/sdram.h>
+#include "sdram.h"
+#include "ccplex.h"
void main(void)
{
@@ -35,9 +36,11 @@ void main(void)
printk(BIOS_INFO, "T132: romstage here\n");
sdram_init(get_sdram_config());
-
printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
+ ccplex_load_mts();
+ printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
+
while (1);
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,