diff options
| -rw-r--r-- | src/cpu/samsung/exynos5420/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/chip.h | 5 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/cpu.c | 14 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/usb.c | 105 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/usb.h | 62 | ||||
| -rw-r--r-- | src/mainboard/google/pit/devicetree.cb | 2 |
6 files changed, 186 insertions, 3 deletions
diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 6f9b91bb62..854040948e 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp-reg.c ramstage-y += fb.c +ramstage-y += usb.c exynos5420_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5420 BL1\n" diff --git a/src/cpu/samsung/exynos5420/chip.h b/src/cpu/samsung/exynos5420/chip.h index 7f1aadce32..f2c710df50 100644 --- a/src/cpu/samsung/exynos5420/chip.h +++ b/src/cpu/samsung/exynos5420/chip.h @@ -20,6 +20,8 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_H #define CPU_SAMSUNG_EXYNOS5420_H +#include "gpio.h" + struct cpu_samsung_exynos5420_config { /* special magic numbers! */ int clkval_f; @@ -34,6 +36,9 @@ struct cpu_samsung_exynos5420_config { int yres; int bpp; + int usb_vbus_gpio; + int usb_hsic_gpio; + u32 lcdbase; }; diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 6e360bf350..d204556239 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -29,6 +29,7 @@ #include "dp-core.h" #include "cpu.h" #include "clk.h" +#include "usb.h" #include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) @@ -119,15 +120,22 @@ static void exynos_displayport_init(device_t dev) ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_init(device_t dev) +static void cpu_enable(device_t dev) { exynos_displayport_init(dev); + ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); set_cpu_id(); +} + +static void cpu_init(device_t dev) +{ printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); + + usb_init(dev); } static void cpu_noop(device_t dev) @@ -137,8 +145,8 @@ static void cpu_noop(device_t dev) static struct device_operations cpu_ops = { .read_resources = cpu_noop, .set_resources = cpu_noop, - .enable_resources = cpu_init, - .init = cpu_noop, + .enable_resources = cpu_enable, + .init = cpu_init, .scan_bus = 0, }; diff --git a/src/cpu/samsung/exynos5420/usb.c b/src/cpu/samsung/exynos5420/usb.c new file mode 100644 index 0000000000..4d0769970a --- /dev/null +++ b/src/cpu/samsung/exynos5420/usb.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include "gpio.h" +#include "power.h" +#include "cpu.h" +#include "usb.h" +#include "chip.h" + +/* Enable VBUS */ +static int usb_vbus_init(int vbus_gpio) +{ + /* Enable VBUS power switch */ + gpio_direction_output(GPIO_X11, 1); + /* VBUS turn ON time */ + mdelay(3); + + return 0; +} + +/* Setup the EHCI host controller. */ + +static void setup_usb_phy(struct usb_phy *usb, int hsic_gpio) +{ + unsigned int hostphy_ctrl0; + + power_enable_usb_phy(); + + /* Setting up host and device simultaneously */ + hostphy_ctrl0 = readl(&usb->usbphyctrl0); + hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | + /* HOST Phy setting */ + HOST_CTRL0_PHYSWRST | + HOST_CTRL0_PHYSWRSTALL | + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESUSPEND | + HOST_CTRL0_FORCESLEEP); + hostphy_ctrl0 |= ( /* Setting up the ref freq */ + CLK_24MHZ << 16 | + /* HOST Phy setting */ + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); + writel(hostphy_ctrl0, &usb->usbphyctrl0); + udelay(10); + clrbits_le32(&usb->usbphyctrl0, + HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); + udelay(20); + + /* EHCI Ctrl setting */ + setbits_le32(&usb->ehcictrl, + EHCICTRL_ENAINCRXALIGN | + EHCICTRL_ENAINCR4 | + EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16); + + /* HSIC USB Hub initialization. */ + // FIXME board specific? + gpio_direction_output(hsic_gpio, 0); + udelay(100); + gpio_direction_output(hsic_gpio, 1); + udelay(5000); + + clrbits_le32(&usb->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST); + udelay(10); + clrbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST); + + /* PHY clock and power setup time */ + // FIXME If this happens more than 50ms before executing the payload, + // we might not need this delay. + mdelay(50); +} + +void usb_init(device_t dev) +{ + struct usb_phy *usb; + struct cpu_samsung_exynos5420_config *conf = dev->chip_info; + + usb_vbus_init(conf->usb_vbus_gpio); + usb = (struct usb_phy *) samsung_get_base_usb_phy(); + setup_usb_phy(usb, conf->usb_hsic_gpio); +} diff --git a/src/cpu/samsung/exynos5420/usb.h b/src/cpu/samsung/exynos5420/usb.h new file mode 100644 index 0000000000..1b7d6357e7 --- /dev/null +++ b/src/cpu/samsung/exynos5420/usb.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5420_USB_H +#define CPU_SAMSUNG_EXYNOS5420_USB_H + +#define CLK_24MHZ 5 + +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) + +#define HOST_CTRL0_FSEL_MASK (7 << 16) + +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) + +/* Register map for PHY control */ +struct usb_phy { + uint32_t usbphyctrl0; + uint32_t usbphytune0; + uint32_t reserved1[2]; + uint32_t hsicphyctrl1; + uint32_t hsicphytune1; + uint32_t reserved2[2]; + uint32_t hsicphyctrl2; + uint32_t hsicphytune2; + uint32_t reserved3[2]; + uint32_t ehcictrl; + uint32_t ohcictrl; + uint32_t usbotgsys; + uint32_t reserved4; + uint32_t usbotgtune; +}; + +void usb_init(device_t dev); + +#endif diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb index 3b6cdb9014..0c687c41c3 100644 --- a/src/mainboard/google/pit/devicetree.cb +++ b/src/mainboard/google/pit/devicetree.cb @@ -30,4 +30,6 @@ chip cpu/samsung/exynos5420 register "left_margin" = "80" register "right_margin" = "48" register "hsync" = "32" + register "usb_vbus_gpio" = "GPIO_X11" + register "usb_hsic_gpio" = "GPIO_E10" end |