diff options
| -rw-r--r-- | src/mainboard/amd/bettong/BiosCallOuts.c | 23 | ||||
| -rw-r--r-- | src/mainboard/amd/bettong/OemCustomize.c | 21 |
2 files changed, 21 insertions, 23 deletions
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index a2eeec7993..0fe8bd5ec7 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -31,7 +31,6 @@ #include "BiosCallOuts.h" #include "northbridge/amd/pi/dimmSpd.h" #include "northbridge/amd/pi/agesawrapper.h" -#include <PlatformMemoryConfiguration.h> #include <boardid.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); @@ -140,25 +139,3 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) #endif return AGESA_SUCCESS; } - -#ifdef __PRE_RAM__ - -const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { - DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), - MOTHER_BOARD_LAYERS (LAYERS_6), - MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), - ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), - CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), - PSO_END -}; - -void OemPostParams(AMD_POST_PARAMS *PostParams) -{ - if (board_id() == 'F') { - PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; - } -} -#endif diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c index a32ea9a424..8d1ad4bdb5 100644 --- a/src/mainboard/amd/bettong/OemCustomize.c +++ b/src/mainboard/amd/bettong/OemCustomize.c @@ -14,6 +14,8 @@ */ #include <northbridge/amd/pi/agesawrapper.h> +#include <PlatformMemoryConfiguration.h> +#include <boardid.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -132,3 +134,22 @@ VOID OemCustomizeInitEarly ( { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; } + +static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MOTHER_BOARD_LAYERS (LAYERS_6), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + PSO_END +}; + +void OemPostParams(AMD_POST_PARAMS *PostParams) +{ + if (board_id() == 'F') { + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + } +} |