diff options
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 59 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 28 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/ramstage.h | 28 |
4 files changed, 117 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 9c2256f973..297d34f176 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -18,7 +18,8 @@ romstage-y += memmap.c romstage-y += reset.c romstage-$(CONFIG_UART_DEBUG) += uart.c -ramstage-y += cbmem.c +ramstage-y += chip.c +ramstage-y += memmap.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c new file mode 100644 index 0000000000..2f893e3d48 --- /dev/null +++ b/src/soc/intel/cannonlake/chip.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <console/console.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <romstage_handoff.h> +#include <soc/ramstage.h> +#include <string.h> + +void soc_init_pre_device(void *chip_info) +{ + /* Perform silicon specific init. */ + fsp_silicon_init(romstage_handoff_is_resume()); +} + +struct chip_operations soc_intel_cannonlake_ops = { + CHIP_NAME("Intel Cannonlake") + .init = &soc_init_pre_device, +}; + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + int i; + FSP_S_CONFIG *params = &supd->FspsConfig; + + /* Set USB OC pin to 0 first */ + for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { + params->Usb2OverCurrentPin[i] = 0; + } + + for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { + params->Usb3OverCurrentPin[i] = 0; + } + + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h new file mode 100644 index 0000000000..bbc58808a3 --- /dev/null +++ b/src/soc/intel/cannonlake/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include <stdint.h> + +struct soc_intel_cannonlake_config { +}; + +typedef struct soc_intel_cannonlake_config config_t; + +#endif diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h new file mode 100644 index 0000000000..4a96185e6b --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <chip.h> +#include <device/device.h> +#include <fsp/api.h> +#include <fsp/util.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void soc_init_pre_device(void *chip_info); + +#endif |