diff options
| -rw-r--r-- | src/mainboard/google/storm/reset.c | 30 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/soc/iomap.h | 4 |
2 files changed, 30 insertions, 4 deletions
diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c index 8020fbfbed..58c52f91d9 100644 --- a/src/mainboard/google/storm/reset.c +++ b/src/mainboard/google/storm/reset.c @@ -1,6 +1,8 @@ /* + * * This file is part of the coreboot project. * + * Copyright (c) 2014, The Linux Foundation. All rights reserved. * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify @@ -17,10 +19,34 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> +#include <soc/iomap.h> #include <reset.h> -void hard_reset(void) +/* Watchdog bite time set to default reset value */ +#define RESET_WDT_BITE_TIME 0x31F3 + +/* Watchdog bark time value is kept larger than the watchdog timeout + * of 0x31F3, effectively disabling the watchdog bark interrupt + */ +#define RESET_WDT_BARK_TIME (5 * RESET_WDT_BITE_TIME) + +static void wdog_reset(void) { - while (1) + printk(BIOS_DEBUG, "\nResetting with watchdog!\n"); + + writel(0, APCS_WDT0_EN); + writel(1, APCS_WDT0_RST); + writel(RESET_WDT_BARK_TIME, APCS_WDT0_BARK_TIME); + writel(RESET_WDT_BITE_TIME, APCS_WDT0_BITE_TIME); + writel(1, APCS_WDT0_EN); + writel(1, APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE); + + for (;;) ; } + +void hard_reset(void) +{ + wdog_reset(); +} diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index 333e2615eb..129b17700c 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -49,9 +49,9 @@ #define clrsetbits_le32_i(addr, clear, set) \ clrsetbits_le32(((void *)(addr)), (clear), (set)) -#define MSM_CLK_CTL_BASE 0x00900000 +#define MSM_CLK_CTL_BASE ((unsigned char *)0x00900000) -#define MSM_TMR_BASE 0x0200A000 +#define MSM_TMR_BASE ((unsigned char *)0x0200A000) #define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) |