diff options
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1b699520ac..07cb8b1669 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -376,6 +376,14 @@ struct soc_intel_skylake_config { /* Enable/Disable VMX feature */ u8 VmxEnable; + /* + * PRMRR size setting with three options + * 0x02000000 - 32MiB + * 0x04000000 - 64MiB + * 0x08000000 - 128MiB + */ + u32 PrmrrSize; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index e478890930..a4bb6849e4 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -139,6 +139,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) m_cfg->RMT = config->Rmt; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = config->VmxEnable; + m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); |