diff options
| -rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.c | 40 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.h | 19 |
2 files changed, 35 insertions, 24 deletions
diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 073e41e645..40b8b532ea 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -30,12 +30,6 @@ #include "fchec.h" #endif -/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ -#define PM_MMIO_BASE 0xfed80300 - int acpi_get_sleep_type(void) { @@ -76,19 +70,19 @@ void hudson_enable(device_t dev) /* turn off the SDHC controller in the PM reg */ u8 reg8; if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) { - reg8 = pm_read8(0xe7); - reg8 &= ~(1 << 0); - pm_write8(0xe7, reg8); + reg8 = pm_read8(PM_HUD_SD_FLASH_CTRL); + reg8 &= ~BIT(0); + pm_write8(PM_HUD_SD_FLASH_CTRL, reg8); } else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) { - reg8 = pm_read8(0xe8); - reg8 &= ~(1 << 0); - pm_write8(0xe8, reg8); + reg8 = pm_read8(PM_YANG_SD_FLASH_CTRL); + reg8 &= ~BIT(0); + pm_write8(PM_YANG_SD_FLASH_CTRL, reg8); } /* remove device 0:14.7 from PCI space */ - reg8 = pm_read8(0xd3); - reg8 &= ~(1 << 6); - pm_write8(0xd3, reg8); + reg8 = pm_read8(PM_MANUAL_RESET); + reg8 &= ~BIT(6); + pm_write8(PM_MANUAL_RESET, reg8); } break; default: @@ -102,24 +96,24 @@ static void hudson_init_acpi_ports(void) * ACPI tables are generated. Enable these ports indiscriminately. */ - pm_write16(0x60, ACPI_PM_EVT_BLK); - pm_write16(0x62, ACPI_PM1_CNT_BLK); - pm_write16(0x64, ACPI_PM_TMR_BLK); - pm_write16(0x68, ACPI_GPE0_BLK); + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); /* CpuControl is in \_PR.CP00, 6 bytes */ - pm_write16(0x66, ACPI_CPU_CONTROL); + pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - pm_write16(0x6a, ACPI_SMI_CTL_PORT); + pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT); hudson_enable_acpi_cmd_smi(); } else { - pm_write16(0x6a, 0); + pm_write16(PM_ACPI_SMI_CMD, 0); } /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn */ - pm_write8(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); + pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2)); } static void hudson_init(void *chip_info) diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6e3157dd14..6c08f2f1b4 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -22,6 +22,12 @@ #include <device/device.h> #include "chip.h" +/* Offsets from ACPI_MMIO_BASE + * This is defined by AGESA, but we don't include AGESA headers to avoid + * polluting the namespace. + */ +#define PM_MMIO_BASE 0xfed80300 + /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 @@ -30,8 +36,19 @@ #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 -#define HUDSON_ACPI_IO_BASE 0x800 +#define PM_SERIRQ_CONF 0x54 +#define PM_EVT_BLK 0x60 +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_CPU_CTRL 0x66 +#define PM_GPE0_BLK 0x68 +#define PM_ACPI_SMI_CMD 0x6A +#define PM_ACPI_CONF 0x74 +#define PM_MANUAL_RESET 0xD3 +#define PM_HUD_SD_FLASH_CTRL 0xE7 +#define PM_YANG_SD_FLASH_CTRL 0xE8 +#define HUDSON_ACPI_IO_BASE 0x800 #define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ |