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-rw-r--r--src/soc/intel/common/block/include/intelblocks/pcie_rp.h15
-rw-r--r--src/soc/intel/common/block/pcie/Makefile.inc3
-rw-r--r--src/soc/intel/common/block/pcie/pcie_helpers.c40
3 files changed, 58 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index ca50b13247..264c43f585 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -3,6 +3,8 @@
#ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
#define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
+#include <stdint.h>
+
/*
* The PCIe Root Ports usually come in groups of up to 8 PCI-device
* functions.
@@ -34,4 +36,17 @@ struct pcie_rp_group {
*/
void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
+/*
+ * Return mask of PCIe root ports that are enabled by mainboard. Mask is set in the same order
+ * as the root ports in pcie_rp_group groups table.
+ *
+ * Thus, the status of first root port in the groups table is indicated by bit 0 in the returned
+ * mask, second root port by bit 1 and so on.
+
+ * 1 in the bit position indicates root port is enabled, whereas 0 indicates root port is
+ * disabled. This function assumes that the maximum count of root ports in the groups table is
+ * <= 32.
+ */
+uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
+
#endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */
diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc
index e2ad685bc3..521ca6b37e 100644
--- a/src/soc/intel/common/block/pcie/Makefile.inc
+++ b/src/soc/intel/common/block/pcie/Makefile.inc
@@ -1,4 +1,7 @@
subdirs-y += ./*
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c
+
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c
diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c
new file mode 100644
index 0000000000..31451d07f6
--- /dev/null
+++ b/src/soc/intel/common/block/pcie/pcie_helpers.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <intelblocks/pcie_rp.h>
+#include <stdint.h>
+
+static uint32_t pcie_slot_enable_mask(unsigned int slot, unsigned int count)
+{
+ uint32_t mask = 0;
+ unsigned int i;
+ const struct device *dev;
+
+ for (i = 0; i < count; i++) {
+ dev = pcidev_on_root(slot, i);
+ if (is_dev_enabled(dev))
+ mask |= BIT(i);
+ }
+
+ return mask;
+}
+
+uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups)
+{
+ uint32_t mask = 0;
+ uint32_t offset = 0;
+ const struct pcie_rp_group *group;
+
+ for (group = groups; group->count; ++group) {
+ if (group->count + offset >= sizeof(mask) * 8) {
+ printk(BIOS_ERR, "ERROR: %s: Root port count greater than mask size!\n",
+ __func__);
+ break;
+ }
+ mask |= pcie_slot_enable_mask(group->slot, group->count) << offset;
+ offset += group->count;
+ }
+
+ return mask;
+}