diff options
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.c | 46 | ||||
| -rw-r--r-- | src/northbridge/intel/e7505/raminit.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/e7505/romstage.c | 27 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/early_smbus.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.h | 1 |
5 files changed, 40 insertions, 43 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 972a2f37ee..7953aca3b1 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1740,28 +1740,38 @@ static void sdram_set_registers(const struct mem_controller *ctrl) d060_control(D060_CMD_1); } -/** - * - * - */ -void e7505_mch_init(const struct mem_controller *memctrl) +static int e7505_mch_is_ready(void) { - timestamp_add_now(TS_BEFORE_INITRAM); - - sdram_set_registers(memctrl); - sdram_set_spd_registers(memctrl); - sdram_enable(memctrl); + uint32_t dword = pci_read_config32(MCHDEV, DRC); + return !!(dword & DRC_DONE); } -void e7505_mch_done(const struct mem_controller *memctrl) +void sdram_initialize(void) { - sdram_post_ecc(memctrl); + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .d0f1 = PCI_DEV(0, 0, 1), + .channel0 = { 0x50, 0x52, 0, 0 }, + .channel1 = { 0x51, 0x53, 0, 0 }, + }, + }; - timestamp_add_now(TS_AFTER_INITRAM); -} + /* If this is a warm boot, some initialisation can be skipped */ + if (!e7505_mch_is_ready()) { -int e7505_mch_is_ready(void) -{ - uint32_t dword = pci_read_config32(MCHDEV, DRC); - return !!(dword & DRC_DONE); + /* The real MCH initialisation. */ + timestamp_add_now(TS_BEFORE_INITRAM); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(memctrl); + + /* Hook for post ECC scrub settings and debug. */ + sdram_post_ecc(memctrl); + + timestamp_add_now(TS_AFTER_INITRAM); + } + + printk(BIOS_DEBUG, "SDRAM is up.\n"); } diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index c65675f820..9aa6eb4b8e 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -30,8 +30,6 @@ struct mem_controller { uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; -void e7505_mch_init(const struct mem_controller *memctrl); -void e7505_mch_done(const struct mem_controller *memctrl); -int e7505_mch_is_ready(void); +void sdram_initialize(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index 6c74c1febf..f506bf4894 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <cbmem.h> -#include <console/console.h> #include <arch/romstage.h> #include <southbridge/intel/i82801dx/i82801dx.h> @@ -23,27 +21,12 @@ void mainboard_romstage_entry(void) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { 0x50, 0x52, 0, 0 }, - .channel1 = { 0x51, 0x53, 0, 0 }, - }, - }; + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i82801dx_early_init(); - /* If this is a warm boot, some initialization can be skipped */ - if (!e7505_mch_is_ready()) { - enable_smbus(); - - /* The real MCH initialisation. */ - e7505_mch_init(memctrl); - - /* Hook for post ECC scrub settings and debug. */ - e7505_mch_done(memctrl); - } - - printk(BIOS_DEBUG, "SDRAM is up.\n"); + sdram_initialize(); cbmem_recovery(0); } diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 77b0aa084b..de0bc93978 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -21,6 +21,11 @@ #include "i82801dx.h" +void i82801dx_early_init(void) +{ + enable_smbus(); +} + void enable_smbus(void) { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 50122d830b..8717e5943b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -35,6 +35,7 @@ #include "chip.h" void i82801dx_enable(struct device *dev); +void i82801dx_early_init(void); void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); |