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-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb3
-rw-r--r--src/soc/intel/alderlake/Kconfig11
-rw-r--r--src/soc/intel/alderlake/chip.h4
3 files changed, 10 insertions, 8 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index f2a8f3779a..0dd1456d42 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -84,9 +84,6 @@ chip soc/intel/alderlake
register "PchPcieRpEnable[2]" = "1"
register "PchPcieRpEnable[3]" = "1"
- # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
- register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
-
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 7289e02032..806c91b334 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -139,10 +139,15 @@ config MAX_ROOT_PORTS
int
default MAX_PCH_ROOT_PORTS
-config MAX_PCIE_CLOCKS
+config MAX_PCIE_CLOCK_SRC
int
- default 10 if SOC_INTEL_ALDERLAKE_PCH_M
- default 12
+ default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 7
+
+config MAX_PCIE_CLOCK_REQ
+ int
+ default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 10
config SMM_TSEG_SIZE
hex
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 70ceba7fdf..0f932ce132 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -131,10 +131,10 @@ struct soc_intel_alderlake_config {
/* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
- uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
+ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */
- uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ];
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];