diff options
| -rw-r--r-- | src/cpu/intel/model_1067x/model_1067x_init.c | 17 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 17 | ||||
| -rw-r--r-- | src/cpu/intel/model_f4x/model_f4x_init.c | 16 | ||||
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/cmos.layout | 1 | ||||
| -rw-r--r-- | src/mainboard/foxconn/g41s-k/cmos.layout | 1 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 22 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 4 |
9 files changed, 2 insertions, 78 deletions
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 8f8af57037..275ff70267 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -19,13 +19,10 @@ #include <device/device.h> #include <string.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mp.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/intel/smm/gen1/smi.h> @@ -280,20 +277,10 @@ static void model_1067x_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Update the microcode */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_update_microcode_from_cbfs(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Setup MTRRs */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { - x86_setup_mtrrs(); - x86_mtrr_check(); - } - /* Enable the local CPU APICs */ setup_lapic(); @@ -318,10 +305,6 @@ static void model_1067x_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(tm2, quad); - - /* Start up my CPU siblings */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a502826c77..16ddcc4c28 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -18,11 +18,8 @@ #include <device/device.h> #include <string.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/hyperthreading.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -132,20 +129,10 @@ static void model_6fx_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Update the microcode */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_update_microcode_from_cbfs(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Setup MTRRs */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { - x86_setup_mtrrs(); - x86_mtrr_check(); - } - /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT @@ -163,10 +150,6 @@ static void model_6fx_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my CPU siblings */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 1b3cfe96e1..941bee1466 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -13,10 +13,7 @@ #include <device/device.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> static void model_f4x_init(struct device *cpu) @@ -24,21 +21,8 @@ static void model_f4x_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { - /* MTRRs are shared between threads */ - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - } - /* Enable the local CPU APICs */ setup_lapic(); - - /* Start up my CPU siblings */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index 57c30ae523..e6df510341 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -56,7 +56,6 @@ entries 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 1 e 2 hyper_threading #425 7 r 0 unused # coreboot config options: northbridge diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index 57c30ae523..e6df510341 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -56,7 +56,6 @@ entries 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 1 e 2 hyper_threading #425 7 r 0 unused # coreboot config options: northbridge diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 4da0e96cbf..749f91d83e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -57,7 +57,6 @@ entries 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 1 e 2 hyper_threading #425 7 r 0 unused # coreboot config options: northbridge diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 117ac03882..6f3546f7f4 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select PARALLEL_MP config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 7de39d1672..4b5a754a1c 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -182,26 +182,6 @@ void northbridge_write_smram(u8 smram) pci_write_config8(dev, D0F0_SMRAM, smram); } -/* - * Really doesn't belong here but will go away with parallel mp init, - * so let it be here for a while... - */ -int cpu_get_apic_id_map(int *apic_id_map) -{ - unsigned int i; - - /* Logical processors (threads) per core */ - const struct cpuid_result cpuid1 = cpuid(1); - /* Read number of cores. */ - const char cores = (cpuid1.ebx >> 16) & 0xf; - - /* TODO in parallel MP cpuid(1).ebx */ - for (i = 0; i < cores; i++) - apic_id_map[i] = i; - - return cores; -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, @@ -215,7 +195,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 3f7095cbdc..b06959aa5b 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -392,10 +392,6 @@ static void i82801jx_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - smm_lock(); #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ |