diff options
| -rwxr-xr-x | src/mainboard/intel/strago/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index ba8968c14c..91337878c2 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -13,6 +13,7 @@ chip soc/intel/braswell register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" ############################################################ # Set the parameters for SiliconInit diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 7b01f0bf11..e302d6cdf5 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -75,6 +75,7 @@ struct soc_intel_braswell_config { UINT8 PcdGttSize; UINT8 PcdLegacySegDecode; UINT8 PcdDvfsEnable; + UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */ /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 2581583065..028469a2ca 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -212,6 +212,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->PcdGttSize = config->PcdGttSize; upd->PcdLegacySegDecode = config->PcdLegacySegDecode; upd->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdCaMirrorEn = config->PcdCaMirrorEn; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, |