diff options
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/stage_cache.c | 32 |
3 files changed, 40 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 6f3546f7f4..7cae91e324 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -30,6 +30,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config CBFS_SIZE hex @@ -47,4 +48,8 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 3118b0980e..cc0a97d052 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -30,5 +30,8 @@ ramstage-y += gma.c ramstage-y += northbridge.c postcar-y += ram_calc.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c endif diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c new file mode 100644 index 0000000000..ff752e5d11 --- /dev/null +++ b/src/northbridge/intel/x4x/stage_cache.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include <cpu/intel/smm/gen1/smi.h> +#include "x4x.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} |