diff options
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 18 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 4 |
2 files changed, 5 insertions, 17 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b923065091..34aec3851b 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <elog.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include "sandybridge.h" @@ -45,22 +44,7 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif + printk(BIOS_DEBUG, " done\n"); } static void sandybridge_setup_graphics(void) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 43316a2f22..064d042e56 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <elog.h> static void early_pch_reset_pmcon(void) { @@ -79,6 +80,9 @@ void mainboard_romstage_entry(unsigned long bist) s3resume = southbridge_detect_s3_resume(); + if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) + boot_count_increment(); + post_code(0x38); mainboard_early_init(s3resume); |