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-rw-r--r--src/mainboard/siemens/chili/Kconfig59
-rw-r--r--src/mainboard/siemens/chili/Kconfig.name6
-rw-r--r--src/mainboard/siemens/chili/Makefile.inc12
-rw-r--r--src/mainboard/siemens/chili/board_info.txt5
-rw-r--r--src/mainboard/siemens/chili/cmos.layout59
-rw-r--r--src/mainboard/siemens/chili/dsdt.asl22
-rw-r--r--src/mainboard/siemens/chili/ec.c99
-rw-r--r--src/mainboard/siemens/chili/ec.h8
-rw-r--r--src/mainboard/siemens/chili/mainboard.c20
-rw-r--r--src/mainboard/siemens/chili/romstage.c42
-rw-r--r--src/mainboard/siemens/chili/variant.h8
-rw-r--r--src/mainboard/siemens/chili/variants/base/Makefile.inc5
-rw-r--r--src/mainboard/siemens/chili/variants/base/board_info.txt1
-rw-r--r--src/mainboard/siemens/chili/variants/base/data.vbtbin0 -> 6144 bytes
-rw-r--r--src/mainboard/siemens/chili/variants/base/devicetree.cb136
-rw-r--r--src/mainboard/siemens/chili/variants/base/gma-mainboard.ads19
-rw-r--r--src/mainboard/siemens/chili/variants/base/gpio.c129
17 files changed, 630 insertions, 0 deletions
diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig
new file mode 100644
index 0000000000..8c919b5631
--- /dev/null
+++ b/src/mainboard/siemens/chili/Kconfig
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_SIEMENS_CHILI_BASE
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_I2C_HID
+ select DRIVERS_UART_8250IO if BOARD_SIEMENS_CHILI_BASE
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM2
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOC_INTEL_CANNONLAKE_PCH_H
+ select SOC_INTEL_COFFEELAKE
+
+config MAINBOARD_DIR
+ string
+ default "siemens/chili"
+
+config MAINBOARD_FAMILY
+ string
+ default "Chili"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Chili base board"
+
+config VARIANT_DIR
+ string
+ default "base" if BOARD_SIEMENS_CHILI_BASE
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config INTEL_GMA_VBT_FILE
+ string
+ default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config CBFS_SIZE
+ hex
+ default 0xb00000
+
+config POST_DEVICE
+ bool
+ default n
+
+endif
diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name
new file mode 100644
index 0000000000..a96a28c1e3
--- /dev/null
+++ b/src/mainboard/siemens/chili/Kconfig.name
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+comment "CHILI"
+
+config BOARD_SIEMENS_CHILI_BASE
+ bool "-> Base board"
diff --git a/src/mainboard/siemens/chili/Makefile.inc b/src/mainboard/siemens/chili/Makefile.inc
new file mode 100644
index 0000000000..abeedf3a85
--- /dev/null
+++ b/src/mainboard/siemens/chili/Makefile.inc
@@ -0,0 +1,12 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c
+ramstage-y += ec.c
+
+smm-y += ec.c
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/siemens/chili/board_info.txt b/src/mainboard/siemens/chili/board_info.txt
new file mode 100644
index 0000000000..cb5b428331
--- /dev/null
+++ b/src/mainboard/siemens/chili/board_info.txt
@@ -0,0 +1,5 @@
+Vendor name: Siemens
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
diff --git a/src/mainboard/siemens/chili/cmos.layout b/src/mainboard/siemens/chili/cmos.layout
new file mode 100644
index 0000000000..4a758d9956
--- /dev/null
+++ b/src/mainboard/siemens/chili/cmos.layout
@@ -0,0 +1,59 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+
+0 120 r 0 reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# coreboot config options: console
+395 4 e 3 debug_level
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+401 1 e 2 vtd
+
+# coreboot config options: pch
+408 2 e 4 power_on_after_fail
+
+# coreboot config options: mainboard
+440 1 e 2 ethernet1
+
+# payload config options
+512 256 s 0 boot_devices
+768 8 h 0 boot_default
+784 1 e 1 cmos_defaults_loaded
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 No
+1 1 Yes
+2 0 Disable
+2 1 Enable
+3 0 Emergency
+3 1 Alert
+3 2 Critical
+3 3 Error
+3 4 Warning
+3 5 Notice
+3 6 Info
+3 7 Debug
+3 8 Spew
+4 0 Disable
+4 1 Enable
+4 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/siemens/chili/dsdt.asl b/src/mainboard/siemens/chili/dsdt.asl
new file mode 100644
index 0000000000..6fd12b15f2
--- /dev/null
+++ b/src/mainboard/siemens/chili/dsdt.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/siemens/chili/ec.c b/src/mainboard/siemens/chili/ec.c
new file mode 100644
index 0000000000..bc0eb7d9ff
--- /dev/null
+++ b/src/mainboard/siemens/chili/ec.c
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <timer.h>
+
+#include "ec.h"
+
+#define EC_STATUS 0x50
+#define EC_RUNNING (1 << 1)
+#define EC_DEVICE_CONTROL_1 0x80
+#define EC_DEVICE_CONTROL_1_PROGAS_ON (1 << 0)
+#define EC_DEVICE_CONTROL_1_BOOMER_ON (1 << 1)
+#define EC_DEVICE_CONTROL_1_BT_RF_ON (1 << 2)
+#define EC_DEVICE_CONTROL_1_TP_ON (1 << 3)
+#define EC_DEVICE_CONTROL_1_LAN2_RST (1 << 6)
+#define EC_DEVICE_CONTROL_2 0x81
+#define EC_DEVICE_CONTROL_2_LAN_1_ON (1 << 0)
+#define EC_DEVICE_CONTROL_2_LAN_2_ON (1 << 1)
+#define EC_DEVICE_CONTROL_2_WLAN_ON (1 << 2)
+#define EC_DEVICE_CONTROL_2_USB_ON (1 << 3)
+#define EC_DEVICE_CONTROL_2_IDE1_ON (1 << 4)
+#define EC_DEVICE_CONTROL_2_IDE2_ON (1 << 5)
+#define EC_DEVICE_CONTROL_2_COM1_ON (1 << 6)
+#define EC_DEVICE_CONTROL_2_MPI_ON (1 << 7)
+
+#define RUNNING_TIMEOUT_MS 3333
+
+static bool ec_running(void)
+{
+ struct stopwatch sw;
+ uint8_t ec_status;
+
+ stopwatch_init_msecs_expire(&sw, RUNNING_TIMEOUT_MS);
+ do
+ ec_status = ec_read(EC_STATUS);
+ while (!(ec_status & EC_RUNNING) && !stopwatch_expired(&sw));
+
+ if (!(ec_status & EC_RUNNING))
+ printk(BIOS_WARNING, "EC not ready after %dms\n", RUNNING_TIMEOUT_MS);
+
+ return !!(ec_status & EC_RUNNING);
+}
+
+void ec_enable_devices(bool enable_usb)
+{
+ uint8_t control_1, control_2;
+
+ if (!ec_running())
+ return;
+
+ control_1 = ec_read(EC_DEVICE_CONTROL_1);
+ control_2 = ec_read(EC_DEVICE_CONTROL_2);
+
+ printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1);
+ printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2);
+
+ control_1 &= ~(EC_DEVICE_CONTROL_1_BT_RF_ON);
+ control_1 |= EC_DEVICE_CONTROL_1_BOOMER_ON;
+
+ control_2 &= ~(EC_DEVICE_CONTROL_2_WLAN_ON | EC_DEVICE_CONTROL_2_USB_ON);
+ control_2 |= EC_DEVICE_CONTROL_2_MPI_ON;
+ if (enable_usb)
+ control_2 |= EC_DEVICE_CONTROL_2_USB_ON;
+
+ ec_write(EC_DEVICE_CONTROL_1, control_1);
+ ec_write(EC_DEVICE_CONTROL_2, control_2);
+
+ printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1));
+ printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2));
+}
+
+void mainboard_smi_sleep(const uint8_t slp_typ)
+{
+ uint8_t control_1, control_2;
+
+ if (slp_typ != ACPI_S5)
+ return;
+
+ if (!ec_running())
+ return;
+
+ control_1 = ec_read(EC_DEVICE_CONTROL_1);
+ control_2 = ec_read(EC_DEVICE_CONTROL_2);
+
+ printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1);
+ printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2);
+
+ control_1 &= ~(EC_DEVICE_CONTROL_1_BOOMER_ON);
+ control_2 &= ~(EC_DEVICE_CONTROL_2_USB_ON | EC_DEVICE_CONTROL_2_MPI_ON);
+
+ ec_write(EC_DEVICE_CONTROL_1, control_1);
+ ec_write(EC_DEVICE_CONTROL_2, control_2);
+
+ printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1));
+ printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2));
+}
diff --git a/src/mainboard/siemens/chili/ec.h b/src/mainboard/siemens/chili/ec.h
new file mode 100644
index 0000000000..50d724ff38
--- /dev/null
+++ b/src/mainboard/siemens/chili/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SIEMENS_CHILI_EC_H
+#define _SIEMENS_CHILI_EC_H
+
+void ec_enable_devices(bool enable_usb);
+
+#endif /* _SIEMENS_CHILI_EC_H */
diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c
new file mode 100644
index 0000000000..42e132dcf9
--- /dev/null
+++ b/src/mainboard/siemens/chili/mainboard.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+#include "ec.h"
+
+static void mainboard_dev_init(struct device *dev)
+{
+ const bool enable_usb = CONFIG(BOARD_SIEMENS_CHILI_BASE);
+ ec_enable_devices(enable_usb);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_dev_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c
new file mode 100644
index 0000000000..9c941c27fd
--- /dev/null
+++ b/src/mainboard/siemens/chili/romstage.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/cnl_memcfg_init.h>
+#include <soc/gpio.h>
+#include <soc/romstage.h>
+
+#include "variant.h"
+
+static void mainboard_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ uint8_t vtd = 1;
+ const struct cnl_mb_cfg cfg = {
+ .spd = {
+ [0] = { READ_SMBUS, { 0x50 << 1 } },
+ [2] = { READ_SMBUS, { 0x52 << 1 } },
+ },
+ .rcomp_resistor = { 121, 75, 100 },
+ .rcomp_targets = { 50, 25, 20, 20, 26 },
+ .dq_pins_interleaved = 1,
+ .vref_ca_config = 2,
+ .ect = 0,
+ };
+ cannonlake_memcfg_init(&memupd->FspmConfig, &cfg);
+ memupd->FspmConfig.EccSupport = 1;
+ memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE;
+
+ get_option(&vtd, "vtd");
+ memupd->FspmTestConfig.VtdDisable = !vtd;
+ get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading");
+
+ mainboard_init();
+}
diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/variant.h
new file mode 100644
index 0000000000..423608f641
--- /dev/null
+++ b/src/mainboard/siemens/chili/variant.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_H_
+#define _VARIANT_H_
+
+const struct pad_config *variant_gpio_table(size_t *num);
+
+#endif /* _VARIANT_H_ */
diff --git a/src/mainboard/siemens/chili/variants/base/Makefile.inc b/src/mainboard/siemens/chili/variants/base/Makefile.inc
new file mode 100644
index 0000000000..86b9433353
--- /dev/null
+++ b/src/mainboard/siemens/chili/variants/base/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/siemens/chili/variants/base/board_info.txt b/src/mainboard/siemens/chili/variants/base/board_info.txt
new file mode 100644
index 0000000000..a5d0991f51
--- /dev/null
+++ b/src/mainboard/siemens/chili/variants/base/board_info.txt
@@ -0,0 +1 @@
+Board name: Chili base board
diff --git a/src/mainboard/siemens/chili/variants/base/data.vbt b/src/mainboard/siemens/chili/variants/base/data.vbt
new file mode 100644
index 0000000000..f79a600525
--- /dev/null
+++ b/src/mainboard/siemens/chili/variants/base/data.vbt
Binary files differ
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
new file mode 100644
index 0000000000..505e9a4852
--- /dev/null
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/cannonlake
+ # FSP configuration
+ register "SaGv" = "SaGv_Enabled"
+ register "RMT" = "0"
+ register "speed_shift_enable" = "1"
+
+ register "PchHdaDspEnable" = "0"
+ register "PchHdaAudioLinkHda" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 01.0 off end # PCIe x16
+ device pci 01.1 off end # PCIe x8
+ device pci 01.2 off end # PCIe x4
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on end # SA Thermal device
+ device pci 05.0 off end # Imaging Processing Unit
+ device pci 08.0 off end # Gaussian mixture model, Neural network accelerator
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 13.0 off end # ISH
+ device pci 14.0 on # USB xHCI
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C?
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC?
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C?
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage?
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue
+ end
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Shared SRAM
+ device pci 14.3 off end # CNVi Wifi
+ device pci 14.5 off end # SDCard
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on # Management Engine Interface 1
+ register "HeciEnabled" = "1"
+ end
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on # SATA
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[0]" = "1" # HDD / SSD
+ register "SataPortsEnable[1]" = "1" # ODD
+ register "SataPortsEnable[3]" = "1" # HDD / SSD
+
+ register "SataPortsDevSlp[0]" = "1" # M.2
+ register "SataPortsDevSlp[2]" = "1" # HDD / SSD
+ end
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on # PCI Express Port 5
+ device pci 00.0 on end # x1 i219
+ register "PcieRpEnable[4]" = "1"
+ register "PcieClkSrcUsage[4]" = "0x70"
+ register "PcieClkSrcClkReq[4]" = "4"
+ register "PcieRpSlotImplemented[4]" = "0"
+ end
+ device pci 1c.5 on # PCI Express Port 6
+ device pci 00.0 on end # x1 i210
+ register "PcieRpEnable[5]" = "1"
+ register "PcieClkSrcUsage[5]" = "5"
+ register "PcieClkSrcClkReq[5]" = "5"
+ register "PcieRpSlotImplemented[5]" = "0"
+ end
+ device pci 1c.6 on # PCI Express Port 7
+ device pci 00.0 on end # x1 M.2 (WLAN / BT)
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpSlotImplemented[6]" = "1"
+ end
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1b.0 on # PCI Express Port 17
+ device pci 00.0 on end # x4 M.2/M
+ register "PcieRpEnable[16]" = "1"
+ register "PcieClkSrcUsage[7]" = "16"
+ register "PcieClkSrcClkReq[7]" = "7"
+ register "PcieRpSlotImplemented[16]" = "1"
+ end
+ device pci 1b.1 off end # PCI Express Port 18
+ device pci 1b.2 off end # PCI Express Port 19
+ device pci 1b.3 off end # PCI Express Port 20
+ device pci 1b.4 off end # PCI Express Port 21
+ device pci 1b.5 off end # PCI Express Port 22
+ device pci 1b.6 off end # PCI Express Port 23
+ device pci 1b.7 off end # PCI Express Port 24
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on # LPC Interface
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 on end # GbE
+ device pci 1f.7 off end # TraceHub
+ end
+end
diff --git a/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads
new file mode 100644
index 0000000000..42a2f2cea4
--- /dev/null
+++ b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1, -- VGA (DVI-I)
+ HDMI2, -- DVI-I
+ DP3, -- DP++
+ HDMI3, -- DP++
+ eDP,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c
new file mode 100644
index 0000000000..65ea037a3a
--- /dev/null
+++ b/src/mainboard/siemens/chili/variants/base/gpio.c
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "variant.h"
+
+static const struct pad_config gpio_table[] = {
+/* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE),
+/* GPP_A16 GPIO */ PAD_NC(GPP_A16, DN_20K),
+/* GPP_B4 GPIO */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
+/* GPP_B5 GPIO */ PAD_NC(GPP_B5, NONE),
+/* GPP_B6 GPIO */ PAD_NC(GPP_B6, NONE),
+/* GPP_B8 GPIO */ PAD_NC(GPP_B8, NONE),
+/* GPP_B10 GPIO */ PAD_NC(GPP_B10, NONE),
+/* GPP_B11 GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP),
+/* GPP_B14 SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+/* GPP_B18 GPIO */ PAD_NC(GPP_B18, NONE),
+/* GPP_B22 GPIO */ PAD_NC(GPP_B22, NONE),
+/* GPP_C2 GPIO */ PAD_NC(GPP_C2, NONE),
+/* GPP_C5 GPIO */ PAD_NC(GPP_C5, NONE),
+/* GPP_C6 SML1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+/* GPP_C7 SML1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+/* GPP_C8 GPIO */ PAD_NC(GPP_C8, NONE),
+/* GPP_C9 GPIO */ PAD_NC(GPP_C9, NONE),
+/* GPP_C12 GPIO */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+/* GPP_C13 GPIO */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+/* GPP_C14 GPIO */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+/* GPP_C15 GPIO */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+/* GPP_C16 I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+/* GPP_C17 I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+/* GPP_C20 UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GPP_C21 UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* GPP_C22 UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+/* GPP_C23 UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+/* GPP_D1 GPIO */ PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+/* GPP_D2 GPIO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+/* GPP_D3 GPIO */ PAD_CFG_GPO(GPP_D3, 1, DEEP),
+/* GPP_D7 GPIO */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST),
+/* GPP_D8 GPIO */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST),
+/* GPP_D17 DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* GPP_D18 DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* GPP_D19 DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* GPP_D20 DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* GPP_D21 GPIO */ PAD_CFG_GPO(GPP_D21, 1, DEEP),
+/* GPP_D22 GPIO */ PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+/* GPP_G1 GPIO */ PAD_CFG_GPO(GPP_G1, 1, PLTRST),
+/* GPP_G2 GPIO */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST),
+/* GPP_G3 GPIO */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT),
+/* I2S1_SFRM GPIO */ PAD_NC(I2S1_SFRM, NONE),
+/* I2S1_TXD GPIO */ PAD_NC(I2S1_TXD, NONE),
+/* GPD0 BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* GPD1 ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+/* GPD7 GPIO */ PAD_CFG_GPO(GPD7, 0, RSMRST),
+/* GPP_K0 GPIO */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST),
+/* GPP_K1 GPIO */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST),
+/* GPP_K2 GPIO */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST),
+/* GPP_K3 GPIO */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST),
+/* GPP_K4 GPIO */ PAD_CFG_GPO(GPP_K4, 1, PWROK),
+/* GPP_K5 GPIO */ PAD_CFG_GPO(GPP_K5, 1, PWROK),
+/* GPP_K8 GPIO */ PAD_NC(GPP_K8, NONE),
+/* GPP_K9 GPIO */ PAD_NC(GPP_K9, NONE),
+/* GPP_K10 GPIO */ PAD_NC(GPP_K10, NONE),
+/* GPP_K11 GPIO */ PAD_NC(GPP_K11, NONE),
+/* GPP_K20 GPIO */ PAD_CFG_GPO(GPP_K20, 1, PLTRST),
+/* GPP_K21 GPIO */ PAD_NC(GPP_K21, NONE),
+/* GPP_H0 GPIO */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST),
+/* GPP_H2 GPIO */ PAD_NC(GPP_H2, NONE),
+/* GPP_H3 GPIO */ PAD_NC(GPP_H3, NONE),
+/* GPP_H10 GPIO */ PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+/* GPP_H15 GPIO */ PAD_CFG_GPO(GPP_H15, 1, DEEP),
+/* GPP_H17 GPIO */ PAD_CFG_GPO(GPP_H17, 1, DEEP),
+/* GPP_E0 SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
+/* GPP_E1 GPIO */ PAD_NC(GPP_E1, NONE),
+/* GPP_E2 GPIO */ PAD_NC(GPP_E2, NONE),
+/* GPP_E4 SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+/* GPP_E5 GPIO */ PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+/* GPP_E6 GPIO */ PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+/* GPP_E8 SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* GPP_E9 USB2_OC0# */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1),
+/* GPP_E10 USB2_OC1# */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1),
+/* GPP_E11 USB2_OC2# */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1),
+/* GPP_E12 GPIO */ PAD_CFG_GPO(GPP_E12, 1, PLTRST),
+/* GPP_F1 GPIO */ PAD_NC(GPP_F1, NONE),
+/* GPP_F2 GPIO */ PAD_NC(GPP_F2, NONE),
+/* GPP_F3 GPIO */ PAD_NC(GPP_F3, NONE),
+/* GPP_F4 GPIO */ PAD_NC(GPP_F4, NONE),
+/* GPP_F5 GPIO */ PAD_CFG_GPO(GPP_F5, 1, PLTRST),
+/* GPP_F6 SATA_DEVSLP4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+/* GPP_F8 GPIO */ PAD_CFG_GPO(GPP_F8, 0, DEEP),
+/* GPP_F9 GPIO */ PAD_CFG_GPO(GPP_F9, 0, DEEP),
+/* GPP_F10 GPIO */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+/* GPP_F13 GPIO */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
+/* GPP_F14 GPIO */ PAD_NC(GPP_F14, NONE),
+/* GPP_F15 USB2_OC4# */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1),
+/* GPP_F16 USB2_OC5# */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1),
+/* GPP_F17 USB2_OC6# */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1),
+/* GPP_F18 GPIO */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT),
+/* GPP_F19 eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* GPP_F20 eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* GPP_F21 eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* GPP_F22 DDPF_CTRLCLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* GPP_F23 DDPF_CTRLDATA */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+/* GPP_I0 DDPB_HPD0 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1),
+/* GPP_I1 DDPB_HPD1 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1),
+/* GPP_I2 DDPB_HPD2 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1),
+/* GPP_I3 DDPB_HPD3 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
+/* GPP_I4 EDP_HPD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+/* GPP_I5 DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
+/* GPP_I6 DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
+/* GPP_I7 DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+/* GPP_I8 DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+/* GPP_I9 DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1),
+/* GPP_I10 DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1),
+/* GPP_J2 n/a */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
+/* GPP_J3 n/a */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1),
+/* GPP_J4 CNV_BRI_DT */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+/* GPP_J5 CNV_BRI_RSP */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1),
+/* GPP_J6 CNV_RGI_DT */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+/* GPP_J7 CNV_RGI_RSP */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+/* GPP_J8 CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+/* GPP_J9 CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+/* GPP_J10 n/a */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1),
+/* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-02 20:43:56 +0000