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-rw-r--r--src/mainboard/google/sarien/chromeos.c4
-rw-r--r--src/soc/intel/cannonlake/Makefile.inc1
-rw-r--r--src/soc/intel/cannonlake/pmc.c65
-rw-r--r--src/soc/intel/icelake/Makefile.inc1
-rw-r--r--src/soc/intel/icelake/pmc.c65
5 files changed, 23 insertions, 113 deletions
diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c
index 8f940ea0a9..6643d9b55d 100644
--- a/src/mainboard/google/sarien/chromeos.c
+++ b/src/mainboard/google/sarien/chromeos.c
@@ -22,8 +22,6 @@
#include <security/tpm/tss.h>
#include <device/device.h>
#include <intelblocks/pmclib.h>
-#include <soc/pmc.h>
-#include <soc/pci_devs.h>
enum rec_mode_state {
REC_MODE_UNINITIALIZED,
@@ -122,5 +120,5 @@ void mainboard_prepare_cr50_reset(void)
{
/* Ensure system powers up after CR50 reset */
if (ENV_RAMSTAGE)
- pmc_set_afterg3(MAINBOARD_POWER_STATE_ON);
+ pmc_soc_set_afterg3_en(true);
}
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 7ff86031cb..724e141d39 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -60,6 +60,7 @@ ramstage-y += xhci.c
smm-y += elog.c
smm-y += p2sb.c
+smm-y += pmc.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += uart.c
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 8eadc8db89..9916fe8812 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -32,35 +32,22 @@
* Set which power state system will be after reapplying
* the power (from G3 State)
*/
-void pmc_set_afterg3(int s5pwr)
+void pmc_soc_set_afterg3_en(const bool on)
{
uint8_t reg8;
- uint8_t *pmcbase = pmc_mmio_regs();
+ uint8_t *const pmcbase = pmc_mmio_regs();
reg8 = read8(pmcbase + GEN_PMCON_A);
-
- switch (s5pwr) {
- case MAINBOARD_POWER_STATE_OFF:
- reg8 |= 1;
- break;
- case MAINBOARD_POWER_STATE_ON:
- reg8 &= ~1;
- break;
- case MAINBOARD_POWER_STATE_PREVIOUS:
- default:
- break;
- }
-
+ if (on)
+ reg8 &= ~SLEEP_AFTER_POWER_FAIL;
+ else
+ reg8 |= SLEEP_AFTER_POWER_FAIL;
write8(pmcbase + GEN_PMCON_A, reg8);
}
-/*
- * Set PMC register to know which state system should be after
- * power reapplied
- */
void pmc_soc_restore_power_failure(void)
{
- pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE);
+ pmc_set_power_failure_state(false);
}
static void pm1_enable_pwrbtn_smi(void *unused)
@@ -119,46 +106,14 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
-static void pch_power_options(void)
-{
- const char *state;
-
- const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
-
- /*
- * Which state do we want to goto after g3 (power restored)?
- * 0 == S5 Soft Off
- * 1 == S0 Full On
- * 2 == Keep Previous State
- */
- switch (pwr_on) {
- case MAINBOARD_POWER_STATE_OFF:
- state = "off";
- break;
- case MAINBOARD_POWER_STATE_ON:
- state = "on";
- break;
- case MAINBOARD_POWER_STATE_PREVIOUS:
- state = "state keep";
- break;
- default:
- state = "undefined";
- }
- pmc_set_afterg3(pwr_on);
- printk(BIOS_INFO, "Set power %s after power failure.\n", state);
-
- /* Set up GPE configuration. */
- pmc_gpe_init();
-}
-
static void pmc_init(void *unused)
{
- config_t *config = config_of_path(SA_DEVFN_ROOT);
+ const config_t *config = config_of_path(SA_DEVFN_ROOT);
rtc_init();
- /* Initialize power management */
- pch_power_options();
+ pmc_set_power_failure_state(true);
+ pmc_gpe_init();
config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc
index cd029343bf..15f7030ba0 100644
--- a/src/soc/intel/icelake/Makefile.inc
+++ b/src/soc/intel/icelake/Makefile.inc
@@ -57,6 +57,7 @@ ramstage-y += sd.c
smm-y += gpio.c
smm-y += p2sb.c
+smm-y += pmc.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += uart.c
diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c
index b1c66b9efc..a66d01fb10 100644
--- a/src/soc/intel/icelake/pmc.c
+++ b/src/soc/intel/icelake/pmc.c
@@ -29,35 +29,22 @@
* Set which power state system will be after reapplying
* the power (from G3 State)
*/
-static void pmc_set_afterg3(int s5pwr)
+void pmc_soc_set_afterg3_en(const bool on)
{
uint8_t reg8;
- uint8_t *pmcbase = pmc_mmio_regs();
+ uint8_t *const pmcbase = pmc_mmio_regs();
reg8 = read8(pmcbase + GEN_PMCON_A);
-
- switch (s5pwr) {
- case MAINBOARD_POWER_STATE_OFF:
- reg8 |= 1;
- break;
- case MAINBOARD_POWER_STATE_ON:
- reg8 &= ~1;
- break;
- case MAINBOARD_POWER_STATE_PREVIOUS:
- default:
- break;
- }
-
+ if (on)
+ reg8 &= ~SLEEP_AFTER_POWER_FAIL;
+ else
+ reg8 |= SLEEP_AFTER_POWER_FAIL;
write8(pmcbase + GEN_PMCON_A, reg8);
}
-/*
- * Set PMC register to know which state system should be after
- * power reapplied
- */
void pmc_soc_restore_power_failure(void)
{
- pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE);
+ pmc_set_power_failure_state(false);
}
static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
@@ -101,46 +88,14 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
-static void pch_power_options(void)
-{
- const char *state;
-
- const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
-
- /*
- * Which state do we want to goto after g3 (power restored)?
- * 0 == S5 Soft Off
- * 1 == S0 Full On
- * 2 == Keep Previous State
- */
- switch (pwr_on) {
- case MAINBOARD_POWER_STATE_OFF:
- state = "off";
- break;
- case MAINBOARD_POWER_STATE_ON:
- state = "on";
- break;
- case MAINBOARD_POWER_STATE_PREVIOUS:
- state = "state keep";
- break;
- default:
- state = "undefined";
- }
- pmc_set_afterg3(pwr_on);
- printk(BIOS_INFO, "Set power %s after power failure.\n", state);
-
- /* Set up GPE configuration. */
- pmc_gpe_init();
-}
-
static void pmc_init(void *unused)
{
- config_t *config = config_of_path(SA_DEVFN_ROOT);
+ const config_t *config = config_of_path(SA_DEVFN_ROOT);
rtc_init();
- /* Initialize power management */
- pch_power_options();
+ pmc_set_power_failure_state(true);
+ pmc_gpe_init();
pmc_set_acpi_mode();
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-02 22:15:07 +0000