summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/mainboard/advansus/a785e-i/romstage.c3
-rw-r--r--src/mainboard/amd/bimini_fam10/romstage.c3
-rw-r--r--src/mainboard/amd/mahogany/romstage.c3
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c3
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c3
-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c3
-rw-r--r--src/mainboard/asus/m4a78-em/romstage.c3
-rw-r--r--src/mainboard/asus/m4a785-m/romstage.c3
-rw-r--r--src/mainboard/asus/m5a88-v/romstage.c3
-rw-r--r--src/mainboard/avalue/eax-785e/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ma785gm/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ma78gm/romstage.c3
-rw-r--r--src/mainboard/iei/kino-780am2-fam10/romstage.c3
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c3
-rw-r--r--src/southbridge/amd/rs780/Makefile.inc2
-rw-r--r--src/southbridge/amd/rs780/early_setup.c58
-rw-r--r--src/southbridge/amd/rs780/rs780.h3
18 files changed, 41 insertions, 67 deletions
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 2c7ec83dd1..e59773f5ad 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -41,7 +41,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <southbridge/amd/sb800/smbus.h>
#include <southbridge/amd/sb800/sb800.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include <arch/early_variables.h>
#include <cbmem.h>
@@ -205,7 +205,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 1ca1d81b26..0c26416e75 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -41,7 +41,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include <spd.h>
@@ -200,7 +200,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 7cc45bf36e..979904a06f 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -47,7 +47,7 @@ int spd_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
@@ -142,6 +142,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
}
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index d292205a49..e5766c8ae9 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
@@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e7e1e2fa15..89d170cb5a 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -45,7 +45,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -201,7 +201,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 135db10dd2..d6a85ccee8 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -49,7 +49,7 @@ int spd_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
@@ -208,6 +208,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
}
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index f616d570fc..6392f8f459 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -46,7 +46,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index d6cc5784ec..dd61c8f7a4 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -47,7 +47,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -217,7 +217,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 2993cb4676..e3f3f3cfee 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -44,7 +44,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include "spd.h"
#include <reset.h>
@@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 913b4602ce..993d078999 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -44,7 +44,7 @@
#include <cbmem.h>
#include "spd.h"
#include <reset.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "southbridge/amd/sb800/early_setup.c"
#include "resourcemap.c"
@@ -205,7 +205,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index b578739106..98bc00fd03 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -43,7 +43,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -212,7 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index a21cf70049..81d4c6b36b 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -43,7 +43,7 @@
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -212,7 +212,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 98d038f5a9..9f4dd441d4 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -214,7 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 141b22bc38..866a9a89bb 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -46,7 +46,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -214,7 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 163b2ebe9d..760fc13aed 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -47,7 +47,7 @@
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
-#include "southbridge/amd/rs780/early_setup.c"
+#include <southbridge/amd/rs780/rs780.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
@@ -219,7 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc
index b02f45bdae..36086e90c2 100644
--- a/src/southbridge/amd/rs780/Makefile.inc
+++ b/src/southbridge/amd/rs780/Makefile.inc
@@ -1,5 +1,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS780),y)
+romstage-y += early_setup.c
+
ramstage-y += rs780.c
ramstage-y += cmn.c
ramstage-y += pcie.c
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index ec6c60236d..fd64eb4bb0 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -13,7 +13,14 @@
* GNU General Public License for more details.
*/
+#include <types.h>
+#include <arch/io.h>
+#include <northbridge/amd/amdmct/mct/mct_d.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+
#include "rev.h"
+#include "rs780.h"
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
#define NBMISC_INDEX 0x60
@@ -31,37 +38,37 @@ static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data)
pci_write_config32(dev, index_reg + 0x4, data);
}
-static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
+u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
}
-static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
}
-static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
+u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
}
-static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
}
-static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
+u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMC_INDEX, (index));
}
-static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
}
-static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -73,7 +80,7 @@ static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -85,7 +92,7 @@ static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -114,7 +121,7 @@ static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,
#endif
-static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
+void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
u8 val)
{
u8 reg_old, reg;
@@ -126,7 +133,7 @@ static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
}
}
-static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
+void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -155,25 +162,6 @@ static u8 cpu_core_number(void)
}
#endif
-static u8 get_nb_rev(pci_devfn_t nb_dev)
-{
- u8 reg;
- reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */
- switch(reg & 3)
- {
- case 0x01:
- reg = REV_RS780_A12;
- break;
- case 0x02:
- reg = REV_RS780_A13;
- break;
- default:
- reg = REV_RS780_A11;
- break;
- }
- return reg;
-}
-
/*****************************************
* Init HT link speed/width for rs780 -- k8 link
* 1: Check CPU Family, Family10?
@@ -198,7 +186,7 @@ static const u8 rs780_ibias[] = {
[0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */
};
-static void rs780_htinit(void)
+void rs780_htinit(void)
{
/*
* About HT, it has been done in enumerate_ht_chain().
@@ -610,16 +598,12 @@ static void rs780_por_init(pci_devfn_t nb_dev)
}
/* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs780_dev8(void)
+void enable_rs780_dev8(void)
{
set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
}
-static void rs780_before_pci_init(void)
-{
-}
-
-static void rs780_early_setup(void)
+void rs780_early_setup(void)
{
pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
printk(BIOS_INFO, "rs780_early_setup()\n");
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index 31bec9a1b4..37c88e2058 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -210,4 +210,7 @@ int cpuidFamily(void);
int is_family0Fh(void);
int is_family10h(void);
void pcie_hide_unused_ports(device_t nb_dev);
+void enable_rs780_dev8(void);
+void rs780_early_setup(void);
+void rs780_htinit(void);
#endif /* __RS780_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 16:27:20 +0000