diff options
| -rw-r--r-- | src/mainboard/intel/kunimitsu/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/pei_data.c | 45 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/romstage.c | 11 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/romstage_fsp20.c | 25 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/spd/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/spd/spd.c | 36 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/spd/spd.h | 26 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/spd/spd_util.c | 118 |
8 files changed, 182 insertions, 83 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 2aa3d956d1..a5789b0bcd 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -187,6 +187,9 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c index 3b0237e373..6a211243a7 100644 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ b/src/mainboard/intel/kunimitsu/pei_data.c @@ -19,47 +19,12 @@ #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include "boardid.h" - -/* PCH_MEM_CFG[3:0] */ -#define MAX_MEMORY_CONFIG 0x10 -#define RCOMP_TARGET_PARAMS 0x5 -#define K4E6E304EE_MEM_ID 0x3 +#include "spd/spd.h" void mainboard_fill_pei_data(struct pei_data *pei_data) { - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 6, 5, 4, 7 }, - { 2, 3, 0, 1, 6, 7, 4, 5 } }; - - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 200, 81, 162 }; - - /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 40, 23, 40 }; - - /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ - static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 40, 21, 40 }; - - - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - if (pei_data->mem_cfg_id == K4E6E304EE_MEM_ID) { - memcpy(pei_data->RcompTarget, StrengthendRcompTarget, - sizeof(StrengthendRcompTarget)); - } else { - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); - } - + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); } diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 84c2b6f534..29ffb61f5c 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -25,16 +25,7 @@ void mainboard_romstage_entry(struct romstage_params *params) { - /* PCH_MEM_CFG[3:0] */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, - ARRAY_SIZE(spd_gpios)); + params->pei_data->mem_cfg_id = get_spd_index(); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 10bdd2108c..d4fd1131f7 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -13,9 +13,30 @@ * GNU General Public License for more details. */ +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" #include <soc/romstage.h> +#include <soc/gpio.h> +#include "spd/spd.h" +#include <string.h> -void mainboard_memory_init_params(struct FSPM_UPD *mupd) +void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + if (mainboard_has_dual_channel_mem()) + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; } diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 0a9cb0f4e4..9856368e7a 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -15,6 +15,7 @@ ## romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c +romstage-y += spd_util.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c index faf67913e2..fe30621316 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.c +++ b/src/mainboard/intel/kunimitsu/spd/spd.c @@ -77,39 +77,13 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) { - char *spd_file; - size_t spd_file_len; - int spd_index, spd_span; + uintptr_t spd_data; + spd_data = mainboard_get_spd_data(); + memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - spd_index = pei_data->mem_cfg_id; - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - /* Assume same memory in both channels */ - spd_span = spd_index * SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN); - - if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN - && spd_index != MIC_SINGLE_CHAN) { - memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN); - printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n"); - } + if (mainboard_has_dual_channel_mem()) + memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); /* Make sure a valid SPD was found */ if (pei_data->spd_data[0][0][0] == 0) diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index cdff9ceacc..f53c9ec9fa 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -15,6 +15,10 @@ */ #ifndef MAINBOARD_SPD_H + +#include <gpio.h> +#include "../gpio.h" + #define MAINBOARD_SPD_H #define SPD_LEN 256 @@ -33,4 +37,26 @@ #define HYNIX_SINGLE_CHAN 0x1 #define SAMSUNG_SINGLE_CHAN 0x4 #define MIC_SINGLE_CHAN 0x5 + +/* PCH_MEM_CFG[3:0] */ +#define MAX_MEMORY_CONFIG 0x10 +#define RCOMP_TARGET_PARAMS 0x5 +#define K4E6E304EE_MEM_ID 0x3 + +static inline int get_spd_index(void) { + /* PCH_MEM_CFG[3:0] */ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); +} +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +uintptr_t mainboard_get_spd_data(void); +int mainboard_has_dual_channel_mem(void); #endif diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c new file mode 100644 index 0000000000..0ce2acf6ff --- /dev/null +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "boardid.h" +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + int mem_cfg_id; + + mem_cfg_id = get_spd_index(); + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + /* Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF */ + static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 21, 40 }; + + + if (mem_cfg_id == K4E6E304EE_MEM_ID) { + memcpy(rcomp_strength_ptr, StrengthendRcompTarget, + sizeof(StrengthendRcompTarget)); + } else { + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); + } + +} + +uintptr_t mainboard_get_spd_data(void) +{ + char* spd_file; + int spd_index, spd_span; + size_t spd_file_len; + + spd_index = get_spd_index(); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!(*spd_file)) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + spd_span = spd_index * SPD_LEN; + return (uintptr_t)(spd_file + spd_span); +} + +int mainboard_has_dual_channel_mem(void) +{ + int spd_index; + + spd_index = get_spd_index(); + + if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN + && spd_index != MIC_SINGLE_CHAN) { + printk(BIOS_INFO, + "Dual channel SPD detected writing second channel\n"); + return 1; + } + return 0; +} |