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-rw-r--r--src/soc/amd/cezanne/Kconfig2
-rw-r--r--src/soc/amd/cezanne/include/soc/iomap.h9
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h8
3 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index fe248c6097..be45de4145 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -13,11 +13,13 @@ config SOC_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select IOAPIC
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+ select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
config EARLY_RESERVED_DRAM_BASE
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
new file mode 100644
index 0000000000..96313eaf3c
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_IOMAP_H
+#define AMD_CEZANNE_IOMAP_H
+
+/* I/O Ranges */
+#define SMB_BASE_ADDR 0xb00
+
+#endif /* AMD_CEZANNE_IOMAP_H */
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
new file mode 100644
index 0000000000..0f26ff0807
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_SOUTHBRIDGE_H
+#define AMD_CEZANNE_SOUTHBRIDGE_H
+
+#include <soc/iomap.h>
+
+#endif /* AMD_CEZANNE_SOUTHBRIDGE_H */