diff options
| -rw-r--r-- | src/southbridge/amd/amd8111/bootblock.c | 43 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/enable_rom.c | 42 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/bootblock.c | 52 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/enable_rom.c | 65 | ||||
| -rw-r--r-- | src/southbridge/broadcom/bcm5785/bootblock.c | 20 | ||||
| -rw-r--r-- | src/southbridge/broadcom/bcm5785/enable_rom.c | 39 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/bootblock.c | 32 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/enable_rom.c | 49 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/bootblock.c | 24 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/enable_rom.c | 40 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/bootblock.c | 37 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/enable_rom.c | 54 |
12 files changed, 196 insertions, 301 deletions
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index a11d1d30f4..3009c0b094 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -1,4 +1,45 @@ -#include "southbridge/amd/amd8111/enable_rom.c" +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ +static void amd8111_enable_rom(void) +{ + u8 byte; + device_t dev; + + dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8111_ISA), 0); + + /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ + + /* Set the 5MB enable bits. */ + byte = pci_io_read_config8(dev, 0x43); + byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ + byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ + pci_io_write_config8(dev, 0x43, byte); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/amd/amd8111/enable_rom.c b/src/southbridge/amd/amd8111/enable_rom.c deleted file mode 100644 index 3e73112b47..0000000000 --- a/src/southbridge/amd/amd8111/enable_rom.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Linux Networx - * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_ids.h> - -/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ -static void amd8111_enable_rom(void) -{ - u8 byte; - device_t dev; - - dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_8111_ISA), 0); - - /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ - - /* Set the 5MB enable bits. */ - byte = pci_io_read_config8(dev, 0x43); - byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ - byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ - pci_io_write_config8(dev, 0x43, byte); -} diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index a5eb2f2fac..70076227bf 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -18,7 +17,52 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/amd/sb600/enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The SB600 power-on default is to map 256K ROM space. + * + * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15. + */ +static void sb600_enable_rom(void) +{ + u8 reg8; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SB600_LPC), 0); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_write_config16(dev, 0x6e, 0xffff); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/amd/sb600/enable_rom.c b/src/southbridge/amd/sb600/enable_rom.c deleted file mode 100644 index b2668420ce..0000000000 --- a/src/southbridge/amd/sb600/enable_rom.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_ids.h> - -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The SB600 power-on default is to map 256K ROM space. - * - * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15. - */ -static void sb600_enable_rom(void) -{ - u8 reg8; - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, - PCI_DEVICE_ID_ATI_SB600_LPC), 0); - - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); - reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); - - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); - - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); -} diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index f51fcd0ff9..cadda53596 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -18,7 +18,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ +static void bcm5785_enable_rom(void) +{ + u8 byte; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, + PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); + + /* Set the 4MB enable bits. */ + byte = pci_read_config8(dev, 0x41); + byte |= 0x0e; + pci_write_config8(dev, 0x41, byte); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/broadcom/bcm5785/enable_rom.c b/src/southbridge/broadcom/bcm5785/enable_rom.c deleted file mode 100644 index 1cd28498b9..0000000000 --- a/src/southbridge/broadcom/bcm5785/enable_rom.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_ids.h> - -/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -static void bcm5785_enable_rom(void) -{ - u8 byte; - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, - PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); - - /* Set the 4MB enable bits. */ - byte = pci_read_config8(dev, 0x41); - byte |= 0x0e; - pci_write_config8(dev, 0x41, byte); -} diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index f83b4073c1..07fa0bcd62 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,35 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/intel/i82371eb/enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> +#include "i82371eb.h" + +static void i82371eb_enable_rom(void) +{ + u16 reg16; + device_t dev; + + /* + * Note: The Intel 82371AB/EB/MB ISA device can be on different + * PCI bus:device.function locations on different boards. + * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. + * But scanning for the PCI IDs (instead of hardcoding + * bus/device/function numbers) works on all boards. + */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); + + /* Enable access to the whole ROM, disable ROM write access. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= LOWER_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ + pci_write_config16(dev, XBCS, reg16); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/intel/i82371eb/enable_rom.c b/src/southbridge/intel/i82371eb/enable_rom.c deleted file mode 100644 index 46b0144f28..0000000000 --- a/src/southbridge/intel/i82371eb/enable_rom.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_ids.h> -#include "i82371eb.h" - -static void i82371eb_enable_rom(void) -{ - u16 reg16; - device_t dev; - - /* - * Note: The Intel 82371AB/EB/MB ISA device can be on different - * PCI bus:device.function locations on different boards. - * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. - * But scanning for the PCI IDs (instead of hardcoding - * bus/device/function numbers) works on all boards. - */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); - - /* Enable access to the whole ROM, disable ROM write access. */ - reg16 = pci_read_config16(dev, XBCS); - reg16 |= LOWER_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE_1MB; - reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ - pci_write_config16(dev, XBCS, reg16); -} diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 6d4b6a4777..29c10c8d0e 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Jonathan Kollasch <jakllsch@kollasch.net> + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,7 +21,26 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#include "southbridge/nvidia/ck804/enable_rom.c" +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +static void ck804_enable_rom(void) +{ + unsigned char byte; + device_t addr; + + /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ + /* Locate the ck804 LPC. */ + addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); + + /* Set the 4MB enable bit. */ + byte = pci_read_config8(addr, 0x88); + byte |= 0x80; + pci_write_config8(addr, 0x88, byte); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/nvidia/ck804/enable_rom.c b/src/southbridge/nvidia/ck804/enable_rom.c deleted file mode 100644 index facf7959eb..0000000000 --- a/src/southbridge/nvidia/ck804/enable_rom.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -static void ck804_enable_rom(void) -{ - unsigned char byte; - device_t addr; - - /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ - /* Locate the ck804 LPC. */ - addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); - - /* Set the 4MB enable bit. */ - byte = pci_read_config8(addr, 0x88); - byte |= 0x80; - pci_write_config8(addr, 0x88, byte); -} diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index 139f93c99d..b2698496fa 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -1,7 +1,10 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +21,37 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/nvidia/mcp55/enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include "mcp55.h" + +static void mcp55_enable_rom(void) +{ + uint8_t byte; + uint16_t word; + device_t addr; + + /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ +#if 0 + /* default MCP55 LPC single */ + addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); +#else +// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0); +#endif + + /* Set the 4MB enable bit bit */ + byte = pci_read_config8(addr, 0x88); + byte |= 0xff; //256K + pci_write_config8(addr, 0x88, byte); + byte = pci_read_config8(addr, 0x8c); + byte |= 0xff; //1M + pci_write_config8(addr, 0x8c, byte); + word = pci_read_config16(addr, 0x90); + word |= 0x7fff; //15M + pci_write_config16(addr, 0x90, word); +} static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/nvidia/mcp55/enable_rom.c b/src/southbridge/nvidia/mcp55/enable_rom.c deleted file mode 100644 index d08b1d486b..0000000000 --- a/src/southbridge/nvidia/mcp55/enable_rom.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include "mcp55.h" - -static void mcp55_enable_rom(void) -{ - uint8_t byte; - uint16_t word; - device_t addr; - - /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ -#if 0 - /* default MCP55 LPC single */ - addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); -#else -// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); - addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0); -#endif - - /* Set the 4MB enable bit bit */ - byte = pci_read_config8(addr, 0x88); - byte |= 0xff; //256K - pci_write_config8(addr, 0x88, byte); - byte = pci_read_config8(addr, 0x8c); - byte |= 0xff; //1M - pci_write_config8(addr, 0x8c, byte); - word = pci_read_config16(addr, 0x90); - word |= 0x7fff; //15M - pci_write_config16(addr, 0x90, word); -} |