diff options
| -rw-r--r-- | src/soc/intel/denverton_ns/cpu.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/msr.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 676fab7cbd..f954411ff2 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +40,11 @@ static void denverton_core_init(struct device *cpu) printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Enable Fast Strings */ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= FAST_STRINGS_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 165856fd7c..825d4cfca8 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -92,6 +92,7 @@ #define PRMRR_SUPPORTED (1 << 12) /* IA32_MISC_ENABLE bits */ +#define FAST_STRINGS_ENABLE_BIT (1 << 0) #define SPEED_STEP_ENABLE_BIT (1 << 16) /* Read BCLK from MSR */ |