diff options
| -rw-r--r-- | src/soc/intel/cannonlake/finalize.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/pmutil.c | 14 |
3 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index bc4ae02d66..e334555ac0 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -85,6 +85,8 @@ static void pch_finalize(void) } pch_handle_sideband(config); + + pmc_clear_pmcon_sts(); } static void soc_finalize(void *unused) diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index c8df25a024..5b85e74bf5 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -169,5 +169,8 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 37d1365660..310a0c69d7 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -142,6 +142,20 @@ void pmc_set_disb(void) write8(addr, disb_val); } +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE |