diff options
| -rw-r--r-- | src/northbridge/intel/pineview/acpi/pineview.asl | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/bootblock.c | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index d32a906835..dccbf49387 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x10000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 1c04c28b98..a67cc1aeb5 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -1,8 +1,10 @@ #include <arch/io.h> #define PCIEXBAR 0x60 +#define MMCONF_256_BUSSES 16 +#define ENABLE 1 static void bootblock_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, - CONFIG_MMCONF_BASE_ADDRESS | 4 | 1); + CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); } |