diff options
| -rw-r--r-- | src/mainboard/google/rush_ryu/Kconfig | 21 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/chromeos.c | 89 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/romstage.c | 2 |
4 files changed, 114 insertions, 0 deletions
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index c489a80920..0b64980a8f 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -22,9 +22,14 @@ if BOARD_GOOGLE_RUSH_RYU config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_SUPPORT + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_I2C + select EC_SOFTWARE_SYNC + select SPI_FLASH select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_4096 + select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string @@ -68,4 +73,20 @@ config BOOT_MEDIA_SPI_CHIP_SELECT help Which chip select to use for boot media. +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x2 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config EC_GOOGLE_CHROMEEC_I2C_BUS + hex + default 1 + endif # BOARD_GOOGLE_RUSH_RYU diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc index 4f50c6be5c..677b5f5ba7 100644 --- a/src/mainboard/google/rush_ryu/Makefile.inc +++ b/src/mainboard/google/rush_ryu/Makefile.inc @@ -31,6 +31,7 @@ bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c +romstage-y += chromeos.c romstage-y += reset.c romstage-y += reset.c romstage-y += romstage.c @@ -39,3 +40,4 @@ romstage-y += sdram_configs.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c +ramstage-y += chromeos.c diff --git a/src/mainboard/google/rush_ryu/chromeos.c b/src/mainboard/google/rush_ryu/chromeos.c new file mode 100644 index 0000000000..401cf9372e --- /dev/null +++ b/src/mainboard/google/rush_ryu/chromeos.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/nvidia/tegra132/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_R1_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* TODO(adurbin): add lid switch */ + + /* Power: active low */ + gpios->gpios[count].port = GPIO_Q0_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = 1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_in_value(GPIO(R1)); +} diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index b2acb5d9aa..e570c99314 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -34,6 +34,8 @@ static const struct pad_config padcfgs[] = { /* EC on I2C2 */ PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_INPUT_ENABLE, I2C2), PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_INPUT_ENABLE, I2C2), + /* WP_L */ + PAD_CFG_GPIO_INPUT(KB_ROW1, PINMUX_PULL_NONE), }; static void configure_clocks(void) |