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-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c20
-rw-r--r--src/southbridge/amd/sr5650/ht.c6
2 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index c8bf8fab52..58507d0866 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -737,16 +737,16 @@ static void amdfam10_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
-#if CONFIG_MMCONF_SUPPORT
- struct resource *res = new_resource(dev, 0xc0010058);
- res->base = CONFIG_MMCONF_BASE_ADDRESS;
- res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
- res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
- ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
-#endif
+ if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) {
+ struct resource *res = new_resource(dev, 0xc0010058);
+ res->base = CONFIG_MMCONF_BASE_ADDRESS;
+ res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
+ ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
+ }
if (is_fam15h()) {
enable_cc6 = 0;
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index 611998552d..b45099f59c 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -157,8 +157,8 @@ static void sr5690_read_resource(struct device *dev)
pci_dev_read_resources(dev);
/* rpr6.2.(1). Write the Base Address Register (BAR) */
- pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
- pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */
+ pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
+ pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */
compact_resources(dev);
}
@@ -166,7 +166,7 @@ static void sr5690_read_resource(struct device *dev)
/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
static void sr5690_set_resources(struct device *dev)
{
- pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
+ pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
pci_dev_set_resources(dev);
}