diff options
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/smmrelocate.c | 17 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 182c5ad49f..cdec3ef999 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index bbdcb68b10..e75e884464 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -9,6 +9,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <console/console.h> @@ -137,8 +138,24 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } |