diff options
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/usb_xhci.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 029da9fb35..7b52ebc3e3 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -448,6 +448,10 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define USBOCM1 0x35a0 /* 32bit */ #define USBOCM2 0x35a4 /* 32bit */ +/* XHCI USB 3.0 */ +#define XUSB2PRM 0xd4 /* 32bit */ +#define USB3PRM 0xdc /* 32bit */ + /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04 diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index eb89a7d64f..3e6ce6b341 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -38,8 +38,8 @@ static void usb_xhci_init(struct device *dev) reg32 |= 1; pci_write_config32(dev, 0x44, reg32); - pci_write_config32(dev, 0xd4, config->xhci_switchable_ports); - pci_write_config32(dev, 0xdc, config->superspeed_capable_ports); + pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports); + pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports); /* Enable clock gating */ reg32 = pci_read_config32(dev, 0x40); |