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-rw-r--r--src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
index d6a12749b7..be052f8c37 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
@@ -13,42 +13,42 @@
* GNU General Public License for more details.
*/
-#define DPTF_CPU_PASSIVE 80
-#define DPTF_CPU_CRITICAL 100
+#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_CRITICAL 105
/* Skin Sensor for CPU VR temperature monitor */
#define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Skin"
-#define DPTF_TSR0_PASSIVE 55
-#define DPTF_TSR0_CRITICAL 70
+#define DPTF_TSR0_PASSIVE 71
+#define DPTF_TSR0_CRITICAL 100
/* Memory Sensor for DDR temperature monitor */
#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "DDR"
-#define DPTF_TSR1_PASSIVE 55
-#define DPTF_TSR1_CRITICAL 80
+#define DPTF_TSR1_PASSIVE 56
+#define DPTF_TSR1_CRITICAL 100
/* M.2 Sensor for Ambient temperature monitor */
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "Ambient"
-#define DPTF_TSR2_PASSIVE 55
-#define DPTF_TSR2_CRITICAL 70
+#define DPTF_TSR2_PASSIVE 90
+#define DPTF_TSR2_CRITICAL 100
#undef DPTF_ENABLE_FAN_CONTROL
#undef DPTF_ENABLE_CHARGER
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
- Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 5000, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 200, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 2000, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 10, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
@@ -58,16 +58,16 @@ Name (MPPC, Package ()
0, /* PowerLimitIndex, 0 for Power Limit 1 */
3000, /* PowerLimitMinimum */
25000, /* PowerLimitMaximum */
- 28000, /* TimeWindowMinimum */
- 32000, /* TimeWindowMaximum */
+ 10000, /* TimeWindowMinimum */
+ 10000, /* TimeWindowMaximum */
100 /* StepSize */
},
Package () { /* Power Limit 2 */
1, /* PowerLimitIndex, 1 for Power Limit 2 */
- 15000, /* PowerLimitMinimum */
+ 3000, /* PowerLimitMinimum */
51000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */
- 32000, /* TimeWindowMaximum */
+ 28000, /* TimeWindowMaximum */
100 /* StepSize */
}
})