intelmetool: Consolidate all model support from upstream

Some of the older chipsets that are known not to have ME at all
were removed for some reason, add them back in.

Also some newer chipsets/ME models were missing, add them in.

Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

2 files changed, 273 insertions, 67 deletions

diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c
index 5a0002596c..37cd357a8c 100644
--- a/util/intelmetool/intelmetool.c
+++ b/util/intelmetool/intelmetool.c
@@ -138,7 +138,12 @@ static int pci_platform_scan(void)
 		if (dev->vendor_id != PCI_VENDOR_ID_INTEL)
 			continue;
 
-		if (PCI_DEV_HAS_ME_DISABLE(dev->device_id)) {
+		if (PCI_DEV_NO_ME(dev->device_id)) {
+			printf(CGRN "Good news, you have a `%s` so you have "
+			       "no ME present at all, continuing...\n\n"
+			       RESET, name);
+			break;
+		} else if (PCI_DEV_HAS_ME_DISABLE(dev->device_id)) {
 			printf(CGRN "Good news, you have a `%s` so ME is "
 			       "present but can be disabled, continuing...\n\n"
 			       RESET, name);
diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h
index 49f053717d..ed86b23e33 100644
--- a/util/intelmetool/intelmetool.h
+++ b/util/intelmetool/intelmetool.h
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
  * Copyright (C) 2009 Carl-Daniel Hailfinger
- * Copyright (C) 2015 Damien Zammit
+ * Copyright (C) 2015-2019 Damien Zammit
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -71,6 +71,76 @@ static inline void print_cap(const char *name, int state)
 
 #define PCI_VENDOR_ID_INTEL 0x8086
 
+// Chipset does not have ME
+#define PCI_DEVICE_ID_INTEL_82810		0x7120
+#define PCI_DEVICE_ID_INTEL_82810_DC		0x7122
+#define PCI_DEVICE_ID_INTEL_82810E_DC		0x7124
+#define PCI_DEVICE_ID_INTEL_82830M		0x3575
+#define PCI_DEVICE_ID_INTEL_82845		0x1a30
+#define PCI_DEVICE_ID_INTEL_82865		0x2570
+#define PCI_DEVICE_ID_INTEL_82915		0x2580
+#define PCI_DEVICE_ID_INTEL_82945P		0x2770
+#define PCI_DEVICE_ID_INTEL_82945GM		0x27a0
+#define PCI_DEVICE_ID_INTEL_82945GSE		0x27ac
+#define PCI_DEVICE_ID_INTEL_82X58		0x3405
+#define PCI_DEVICE_ID_INTEL_ATOM_DXXX		0xa000
+#define PCI_DEVICE_ID_INTEL_I63XX		0x2670
+#define PCI_DEVICE_ID_INTEL_I5000X		0x25c0
+#define PCI_DEVICE_ID_INTEL_I5000Z		0x25d0
+#define PCI_DEVICE_ID_INTEL_I5000V		0x25d4
+#define PCI_DEVICE_ID_INTEL_I5000P		0x25d8
+#define PCI_DEVICE_ID_INTEL_82443LX		0x7180
+#define PCI_DEVICE_ID_INTEL_82443BX		0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP	0x7192
+#define PCI_DEVICE_ID_INTEL_82371XX		0x7110
+#define PCI_DEVICE_ID_INTEL_ICH			0x2410
+#define PCI_DEVICE_ID_INTEL_ICH0		0x2420
+#define PCI_DEVICE_ID_INTEL_ICH2		0x2440
+#define PCI_DEVICE_ID_INTEL_ICH4		0x24c0
+#define PCI_DEVICE_ID_INTEL_ICH4M		0x24cc
+#define PCI_DEVICE_ID_INTEL_ICH5		0x24d0
+#define PCI_DEVICE_ID_INTEL_ICH6		0x2640
+#define PCI_DEVICE_ID_INTEL_ICH7DH		0x27b0
+#define PCI_DEVICE_ID_INTEL_ICH7		0x27b8
+#define PCI_DEVICE_ID_INTEL_ICH7M		0x27b9
+#define PCI_DEVICE_ID_INTEL_ICH7MDH		0x27bd
+#define PCI_DEVICE_ID_INTEL_NM10		0x27bc
+
+#define PCI_DEV_NO_ME(x) ( \
+	((x) == PCI_DEVICE_ID_INTEL_82810) || \
+	((x) == PCI_DEVICE_ID_INTEL_82810_DC) || \
+	((x) == PCI_DEVICE_ID_INTEL_82810E_DC) || \
+	((x) == PCI_DEVICE_ID_INTEL_82830M) || \
+	((x) == PCI_DEVICE_ID_INTEL_82845) || \
+	((x) == PCI_DEVICE_ID_INTEL_82865) || \
+	((x) == PCI_DEVICE_ID_INTEL_82915) || \
+	((x) == PCI_DEVICE_ID_INTEL_82945P) || \
+	((x) == PCI_DEVICE_ID_INTEL_82945GM) || \
+	((x) == PCI_DEVICE_ID_INTEL_82945GSE) || \
+	((x) == PCI_DEVICE_ID_INTEL_82X58) || \
+	((x) == PCI_DEVICE_ID_INTEL_ATOM_DXXX) || \
+	((x) == PCI_DEVICE_ID_INTEL_I63XX) || \
+	((x) == PCI_DEVICE_ID_INTEL_I5000X) || \
+	((x) == PCI_DEVICE_ID_INTEL_I5000Z) || \
+	((x) == PCI_DEVICE_ID_INTEL_I5000V) || \
+	((x) == PCI_DEVICE_ID_INTEL_I5000P) || \
+	((x) == PCI_DEVICE_ID_INTEL_82443LX) || \
+	((x) == PCI_DEVICE_ID_INTEL_82443BX) || \
+	((x) == PCI_DEVICE_ID_INTEL_82443BX_NO_AGP) || \
+	((x) == PCI_DEVICE_ID_INTEL_82371XX) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH0) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH2) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH4) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH4M) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH5) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH6) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH7DH) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH7) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH7M) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH7MDH) || \
+	((x) == PCI_DEVICE_ID_INTEL_NM10))
+
 // Definitely has ME and can be disabled
 #define PCI_DEVICE_ID_INTEL_ICH8ME		0x2811
 #define PCI_DEVICE_ID_INTEL_ICH9ME		0x2917
@@ -79,7 +149,7 @@ static inline void print_cap(const char *name, int state)
 #define PCI_DEV_HAS_ME_DISABLE(x) ( \
 	((x) == PCI_DEVICE_ID_INTEL_ICH8ME) || \
 	((x) == PCI_DEVICE_ID_INTEL_ICH9ME) || \
-	((x) == PCI_DEVICE_ID_INTEL_ICH9M  ))
+	((x) == PCI_DEVICE_ID_INTEL_ICH9M))
 
 // Definitely has ME and is very difficult to remove
 #define PCI_DEVICE_ID_INTEL_ICH10R		0x3a16
@@ -130,70 +200,185 @@ static inline void print_cap(const char *name, int state)
 #define PCI_DEVICE_ID_INTEL_HM75		0x1e5d
 #define PCI_DEVICE_ID_INTEL_HM70		0x1e5e
 #define PCI_DEVICE_ID_INTEL_NM70		0x1e5f
-#define PCI_DEVICE_ID_INTEL_QM87		0x8c4f
 #define PCI_DEVICE_ID_INTEL_DH89XXCC		0x2310
 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL	0x9c41
 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM	0x9c43
 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE	0x9c45
-#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP	0x9cc5
+#define PCI_DEVICE_ID_INTEL_H81			0x8c5c
+#define PCI_DEVICE_ID_INTEL_B85			0x8c50
+#define PCI_DEVICE_ID_INTEL_Q85			0x8c4c
+#define PCI_DEVICE_ID_INTEL_Q87			0x8c4e
+#define PCI_DEVICE_ID_INTEL_QM87		0x8c4f
+#define PCI_DEVICE_ID_INTEL_H87			0x8c4a
+#define PCI_DEVICE_ID_INTEL_HM87		0x8c4b
+#define PCI_DEVICE_ID_INTEL_Z87			0x8c44
 #define PCI_DEVICE_ID_INTEL_X99			0x8d47
+#define PCI_DEVICE_ID_INTEL_WILDCAT_LP1		0x9cc1
+#define PCI_DEVICE_ID_INTEL_WILDCAT_LP2		0x9cc2
+#define PCI_DEVICE_ID_INTEL_WILDCAT_LP3		0x9cc3
+#define PCI_DEVICE_ID_INTEL_WILDCAT_LP4		0x9cc5
+#define PCI_DEVICE_ID_INTEL_WILDCAT_LP5		0x9cc6
+#define PCI_DEVICE_ID_INTEL_WILDCAT_LP6		0x9cc7
+#define PCI_DEVICE_ID_INTEL_WILDCAT_LP7		0x9cc9
+#define PCI_DEVICE_ID_INTEL_SUNRISE_LP1		0x9d43
+#define PCI_DEVICE_ID_INTEL_SUNRISE_LP2		0x9d48
+#define PCI_DEVICE_ID_INTEL_SUNRISE_LP3		0x9d4e
+#define PCI_DEVICE_ID_INTEL_SUNRISE_LP4		0x9d56
+#define PCI_DEVICE_ID_INTEL_SUNRISE_LP5		0x9d58
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H0		0xa140
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H1		0xa141
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H2		0xa142
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H3		0xa143
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H4		0xa144
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H5		0xa145
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H6		0xa146
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H7		0xa147
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H8		0xa148
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H9		0xa149
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H10		0xa14a
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H11		0xa14b
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H12		0xa14c
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H13		0xa14d
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H14		0xa14e
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H15		0xa14f
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H16		0xa150
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H17		0xa151
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H18		0xa152
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H19		0xa153
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H20		0xa154
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H21		0xa155
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H22		0xa156
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H23		0xa157
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H24		0xa158
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H25		0xa159
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H26		0xa15a
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H27		0xa15b
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H28		0xa15c
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H29		0xa15d
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H30		0xa15e
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H31		0xa15f
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_1		0xa1c1
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_2		0xa1c2
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_3		0xa1c3
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_4		0xa1c4
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_5		0xa1c5
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_6		0xa1c6
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_7		0xa1c7
 
 #define PCI_DEV_HAS_ME_DIFFICULT(x) ( \
 	((x) == PCI_DEVICE_ID_INTEL_ICH10R) || \
 	((x) == PCI_DEVICE_ID_INTEL_3400_DESKTOP) || \
 	((x) == PCI_DEVICE_ID_INTEL_3400_MOBILE) || \
-	((x) == PCI_DEVICE_ID_INTEL_P55	) || \
-	((x) == PCI_DEVICE_ID_INTEL_PM55	) || \
-	((x) == PCI_DEVICE_ID_INTEL_H55	) || \
-	((x) == PCI_DEVICE_ID_INTEL_QM57	) || \
-	((x) == PCI_DEVICE_ID_INTEL_H57	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM55	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Q57	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM57	) || \
+	((x) == PCI_DEVICE_ID_INTEL_P55) || \
+	((x) == PCI_DEVICE_ID_INTEL_PM55) || \
+	((x) == PCI_DEVICE_ID_INTEL_H55) || \
+	((x) == PCI_DEVICE_ID_INTEL_QM57) || \
+	((x) == PCI_DEVICE_ID_INTEL_H57) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM55) || \
+	((x) == PCI_DEVICE_ID_INTEL_Q57) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM57) || \
 	((x) == PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF) || \
-	((x) == PCI_DEVICE_ID_INTEL_B55_A	) || \
-	((x) == PCI_DEVICE_ID_INTEL_QS57	) || \
-	((x) == PCI_DEVICE_ID_INTEL_3400	) || \
-	((x) == PCI_DEVICE_ID_INTEL_3420	) || \
-	((x) == PCI_DEVICE_ID_INTEL_3450	) || \
-	((x) == PCI_DEVICE_ID_INTEL_B55_B	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Z68	) || \
-	((x) == PCI_DEVICE_ID_INTEL_P67	) || \
-	((x) == PCI_DEVICE_ID_INTEL_UM67	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM65	) || \
-	((x) == PCI_DEVICE_ID_INTEL_H67	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM67	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Q65	) || \
-	((x) == PCI_DEVICE_ID_INTEL_QS67	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Q67	) || \
-	((x) == PCI_DEVICE_ID_INTEL_QM67	) || \
-	((x) == PCI_DEVICE_ID_INTEL_B65	) || \
-	((x) == PCI_DEVICE_ID_INTEL_C202	) || \
-	((x) == PCI_DEVICE_ID_INTEL_C204	) || \
-	((x) == PCI_DEVICE_ID_INTEL_C206	) || \
-	((x) == PCI_DEVICE_ID_INTEL_H61	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Z77	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Z75	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Q77	) || \
-	((x) == PCI_DEVICE_ID_INTEL_Q75	) || \
-	((x) == PCI_DEVICE_ID_INTEL_B75	) || \
-	((x) == PCI_DEVICE_ID_INTEL_H77	) || \
-	((x) == PCI_DEVICE_ID_INTEL_C216	) || \
-	((x) == PCI_DEVICE_ID_INTEL_QM77	) || \
-	((x) == PCI_DEVICE_ID_INTEL_QS77	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM77	) || \
-	((x) == PCI_DEVICE_ID_INTEL_UM77	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM76	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM75	) || \
-	((x) == PCI_DEVICE_ID_INTEL_HM70	) || \
-	((x) == PCI_DEVICE_ID_INTEL_NM70	) || \
-	((x) == PCI_DEVICE_ID_INTEL_QM87	) || \
-	((x) == PCI_DEVICE_ID_INTEL_DH89XXCC	) || \
-	((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL	) || \
-	((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM	) || \
-	((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE	) || \
-	((x) == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP	) || \
-	((x) == PCI_DEVICE_ID_INTEL_X99	))
+	((x) == PCI_DEVICE_ID_INTEL_B55_A) || \
+	((x) == PCI_DEVICE_ID_INTEL_QS57) || \
+	((x) == PCI_DEVICE_ID_INTEL_3400) || \
+	((x) == PCI_DEVICE_ID_INTEL_3420) || \
+	((x) == PCI_DEVICE_ID_INTEL_3450) || \
+	((x) == PCI_DEVICE_ID_INTEL_B55_B) || \
+	((x) == PCI_DEVICE_ID_INTEL_Z68) || \
+	((x) == PCI_DEVICE_ID_INTEL_P67) || \
+	((x) == PCI_DEVICE_ID_INTEL_UM67) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM65) || \
+	((x) == PCI_DEVICE_ID_INTEL_H67) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM67) || \
+	((x) == PCI_DEVICE_ID_INTEL_Q65) || \
+	((x) == PCI_DEVICE_ID_INTEL_QS67) || \
+	((x) == PCI_DEVICE_ID_INTEL_Q67) || \
+	((x) == PCI_DEVICE_ID_INTEL_QM67) || \
+	((x) == PCI_DEVICE_ID_INTEL_B65) || \
+	((x) == PCI_DEVICE_ID_INTEL_C202) || \
+	((x) == PCI_DEVICE_ID_INTEL_C204) || \
+	((x) == PCI_DEVICE_ID_INTEL_C206) || \
+	((x) == PCI_DEVICE_ID_INTEL_H61) || \
+	((x) == PCI_DEVICE_ID_INTEL_Z77) || \
+	((x) == PCI_DEVICE_ID_INTEL_Z75) || \
+	((x) == PCI_DEVICE_ID_INTEL_Q77) || \
+	((x) == PCI_DEVICE_ID_INTEL_Q75) || \
+	((x) == PCI_DEVICE_ID_INTEL_B75) || \
+	((x) == PCI_DEVICE_ID_INTEL_H77) || \
+	((x) == PCI_DEVICE_ID_INTEL_C216) || \
+	((x) == PCI_DEVICE_ID_INTEL_QM77) || \
+	((x) == PCI_DEVICE_ID_INTEL_QS77) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM77) || \
+	((x) == PCI_DEVICE_ID_INTEL_UM77) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM76) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM75) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM70) || \
+	((x) == PCI_DEVICE_ID_INTEL_NM70) || \
+	((x) == PCI_DEVICE_ID_INTEL_DH89XXCC) || \
+	((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL) || \
+	((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM) || \
+	((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE) || \
+	((x) == PCI_DEVICE_ID_INTEL_H81) || \
+	((x) == PCI_DEVICE_ID_INTEL_B85) || \
+	((x) == PCI_DEVICE_ID_INTEL_Q85) || \
+	((x) == PCI_DEVICE_ID_INTEL_Q87) || \
+	((x) == PCI_DEVICE_ID_INTEL_QM87) || \
+	((x) == PCI_DEVICE_ID_INTEL_H87) || \
+	((x) == PCI_DEVICE_ID_INTEL_HM87) || \
+	((x) == PCI_DEVICE_ID_INTEL_Z87) || \
+	((x) == PCI_DEVICE_ID_INTEL_X99) || \
+	((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP1) || \
+	((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP2) || \
+	((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP3) || \
+	((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP4) || \
+	((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP5) || \
+	((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP6) || \
+	((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP7) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP1) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP2) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP3) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP4) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP5) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H0) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H3) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H4) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H5) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H6) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H7) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H8) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H9) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H10) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H11) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H12) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H13) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H14) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H15) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H16) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H17) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H18) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H19) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H20) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H21) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H22) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H23) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H24) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H25) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H26) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H27) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H28) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H29) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H30) || \
+	((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H31) || \
+	((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_1) || \
+	((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_2) || \
+	((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_3) || \
+	((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_4) || \
+	((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_5) || \
+	((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_6) || \
+	((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_7) || \
+	0)
 
 // Not sure if ME present, but should be able to disable it easily
 #define PCI_DEVICE_ID_INTEL_ICH8		0x2810
@@ -204,12 +389,12 @@ static inline void print_cap(const char *name, int state)
 #define PCI_DEVICE_ID_INTEL_ICH9		0x2918
 
 #define PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(x) ( \
-	((x) == PCI_DEVICE_ID_INTEL_ICH8	) || \
-	((x) == PCI_DEVICE_ID_INTEL_ICH8M	) || \
-	((x) == PCI_DEVICE_ID_INTEL_ICH9DH	) || \
-	((x) == PCI_DEVICE_ID_INTEL_ICH9DO	) || \
-	((x) == PCI_DEVICE_ID_INTEL_ICH9R	) || \
-	((x) == PCI_DEVICE_ID_INTEL_ICH9	))
+	((x) == PCI_DEVICE_ID_INTEL_ICH8) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH8M) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH9DH) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH9DO) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH9R) || \
+	((x) == PCI_DEVICE_ID_INTEL_ICH9))
 
 // Not sure at all
 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC	0x8119
@@ -219,6 +404,7 @@ static inline void print_cap(const char *name, int state)
 	((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC) || \
 	((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO))
 
+// ME PCI IDs (HECI)
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_1	0x1C3A /* Cougar Point */
 #define PCI_DEVICE_ID_INTEL_PATSBURG_1	0x1D3A /* C600/X79 Patsburg */
 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_1	0x1CBA /* Panther Point */
@@ -258,9 +444,16 @@ static inline void print_cap(const char *name, int state)
 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_4 0x9C3A /* Lynx Point LP */
 #define PCI_DEVICE_ID_INTEL_WILDCAT_1 0x9CBA /* Wildcat Point LP */
 #define PCI_DEVICE_ID_INTEL_WILDCAT_2 0x9CBB /* Wildcat Point LP 2 */
-#define PCI_DEVICE_ID_INTEL_SUNRISE_H1 0xa13a /* SUNRISE Point-H 1 */
-#define PCI_DEVICE_ID_INTEL_SUNRISE_H2 0xa13b /* SUNRISE Point-H 2 */
 #define PCI_DEVICE_ID_INTEL_SUNRISE_LP 0x9d3a /* SUNRISE Point-LP */
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME 0xa13a /* SUNRISE Point-H 1 */
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME 0xa13b /* SUNRISE Point-H 2 */
+#define PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME 0xA13E /* SUNRISE Point-H 3 */
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME1 0xA1BA /* CSME Lewisburg #1 */
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME2 0xA1BB /* CSME Lewisburg #2 */
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME3 0xA1BE /* CSME Lewisburg #3 */
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE1 0xA1F8 /* IE Lewisburg #1 */
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE2 0xA1F9 /* IE Lewisburg #2 */
+#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE3 0xA1FC /* IE Lewisburg #3 */
 
 #define PCI_DEV_HAS_SUPPORTED_ME(x) ( \
 	((x) ==  PCI_DEVICE_ID_INTEL_COUGARPOINT_1) || \
@@ -302,9 +495,17 @@ static inline void print_cap(const char *name, int state)
 	((x) ==  PCI_DEVICE_ID_INTEL_LYNXPOINT_4) || \
 	((x) ==  PCI_DEVICE_ID_INTEL_WILDCAT_1) || \
 	((x) ==  PCI_DEVICE_ID_INTEL_WILDCAT_2) || \
-	((x) ==  PCI_DEVICE_ID_INTEL_SUNRISE_H1) || \
-	((x) ==  PCI_DEVICE_ID_INTEL_SUNRISE_H2) || \
-	((x) ==  PCI_DEVICE_ID_INTEL_SUNRISE_LP))
+	((x) ==  PCI_DEVICE_ID_INTEL_SUNRISE_LP) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_LEWISBURG_CSME1) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_LEWISBURG_CSME2) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_LEWISBURG_CSME3) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_LEWISBURG_IE1) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_LEWISBURG_IE2) || \
+	((x) ==  PCI_DEVICE_ID_INTEL_LEWISBURG_IE3) || \
+	0)
 
 #define BOOTGUARD_DISABLED 0x400000000
 #define BOOTGUARD_ENABLED_VERIFIED_MODE 0x100000000