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authorFehér Roland Ádám <feherneoh@gmail.com>2018-10-17 18:41:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 19:42:11 +0000
commitd5a8155f1b90531201ae578e019182823614bcea (patch)
treea4e627043783e167e140621a171143a6a4fbe0fc /util
parent967b84d5ea78886f0f076c19f998650fcb94288e (diff)
util/inteltool: Fix LynxPoint (non-LP) GPIO register map
The GPIO register dumper code for the LynxPoint family PCH chips (Intel 8 Series and C220 Series) was incorrectly using a shortened version of the LynxPoint-LP GPIO register map. Switched to the correct register map for the affected chipsets. Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com> Reviewed-on: https://review.coreboot.org/29167 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
-rw-r--r--util/inteltool/gpio.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index c38051c911..b4225a7e0e 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -869,9 +869,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_C226:
case PCI_DEVICE_ID_INTEL_H81:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
- gpio_registers = lynxpoint_lp_gpio_registers;
- /* Shares register locations but has less of them */
- size = 29;
+ gpio_registers = pch_gpio_registers;
+ size = ARRAY_SIZE(pch_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_3400:
case PCI_DEVICE_ID_INTEL_3420: