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authorFelix Held <felix-coreboot@felixheld.de>2022-03-07 17:03:27 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-19 18:26:56 +0000
commitb9ee6f351b4552f024edee3f1e1d72a4a09ec45a (patch)
treed09e812ab6cd5bec8de3150310d731893ce324fd /util
parent7c477a9d1afe324050da6185ab3d22271c94fd7b (diff)
mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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