diff options
| author | Nico Huber <nico.h@gmx.de> | 2021-01-08 17:10:17 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-10 15:49:24 +0000 |
| commit | 03d9298490b452e53a9568d13c7e8c0119bb2e74 (patch) | |
| tree | f96b3b3b5a55278a66fd0c6a11821296058ab22e /util | |
| parent | 15e5e514613bbf25ca5cd5cba81bde31b4085d0b (diff) | |
superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
There were several default values given for GPIO data and status
registers. As all GPIO are configured as inputs by default, we
can't predict the values of these registers, hence set their
default values to NANA.
Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Clay Daniels <clay.daniels.jr@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util')
| -rw-r--r-- | util/superiotool/nuvoton.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index d2b72f2634..ffd12be165 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -538,13 +538,13 @@ static const struct superio_registers reg_table[] = { {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, {0x07, "GPIO 6, GPIO 7, GPIO 8", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, - {0x00,0x7f,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x7f,NANA,0x00,NANA,0xff,NANA,0x00,NANA,0x00,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x08, "WDT1, WDT_MEM, GPIO 0, GPIO 1", {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfe,0xff,EOT}, - {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x00,0x00,0xff,NANA,0x00,NANA,0x00,0xff,NANA,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x09, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,0xfe,EOT}, - {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0xff,NANA,0x00,NANA,0x7f,NANA,0x00,NANA,NANA,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x0a, "ACPI", {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xec,0xed,0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfc,0xfe,EOT}, {0x01,0x00,0x00,0x00,0x00,0x02,0x1a,0x00,0x00,0x00,0x00,0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, |