diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2008-10-09 23:56:11 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-10-09 23:56:11 +0000 |
| commit | 0323a2b8f502767d42486f1c58ab1b9a02e51301 (patch) | |
| tree | 6d16a2661b1f6453ffb1734a0e663f86df86cafc /util | |
| parent | ea7b518ec087ff7847ba2ff8b717305db4c14ab9 (diff) | |
Add Fintek F71882FG support (trivial).
Tested on actual hardware, the MSI K9AG Neo2-Digital (MS-7368).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util')
| -rw-r--r-- | util/superiotool/fintek.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index ea3bdb157a..fc255e733b 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -35,6 +35,48 @@ static const struct superio_registers reg_table[] = { {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */ {EOT}}}, {0x4105, "F71882FG/F71883FG", { /* Same ID? Datasheet typo? */ + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a, + 0x2b,0x2c,0x2d,EOT}, + {0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x08,0x08,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x00,0x83,EOT}}, + {0x6, "GPIO", + {0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0, + 0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2, + 0xf3,EOT}, + {0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00, + 0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA, + 0x00,EOT}}, + {0x7, "VID", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x7, "SPI", + {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, + 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI", + {0x30,0xf0,0xf1,0xf4,0xf5,EOT}, + {0x00,0x00,0x01,0x06,0x1c,EOT}}, {EOT}}}, {0x0604, "F71805F/FG", { /* We assume reserved bits are read as 0. */ |