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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-17 18:08:40 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-02-23 21:36:21 +0100
commitb5a8a13bde537893d1bf150b2d90156e4b855374 (patch)
treeb9ac3ba97d1dc10aa04bf53c26711bd073e3cb75 /util
parent07354235df303c0c1ea3845f5325993a089b4150 (diff)
pcengines/apu1: Fix 0:15.x PCIe root ports
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done to only advertise x1 lane width for PCIe link 0:15.0. Hide functions of PCIe links that have no slots connected. Our PCI infrastructure does not support bridge devices that are set off in devicetree but remain visible in the PCI hardware tree. Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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