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authorAaron Durbin <adurbin@chromium.org>2013-03-26 12:47:47 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-29 19:59:53 +0100
commit77a5b4046ab7e7bee887990b342a7356554fd391 (patch)
tree81e6d965976a65dd62899459a41a75a48033d625 /util
parent9b027fe5b028011593c98d2af8727199b74d3e4c (diff)
x86: mtrr: add CONFIG_CACHE_ROM support
The CONFIG_CACHE_ROM support in the MTRR code allocates an MTRR specifically for setting up write-protect cachine of the ROM. It is assumed that CONFIG_ROM_SIZE is the size of the ROM and the whole area should be cached just under 4GiB. If enabled, the MTRR code will allocate but not enable rom caching. It is up to the callers of the MTRR code to explicitly enable (and disable afterwards) through the use of 2 new functions: - x86_mtrr_enable_rom_caching() - x86_mtrr_disable_rom_caching() Additionally, the CACHE_ROM option is exposed to the config menu so that it is not just selected by the chipset or board. The reasoning is that through a multitude of options CACHE_ROM may not be appropriate for enabling. Change-Id: I4483df850f442bdcef969ffeaf7608ed70b88085 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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