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authorMichał Żygowski <michal.zygowski@3mdeb.com>2018-07-05 16:53:44 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-10 09:53:22 +0000
commit654a45d2ad55fe6ea0a99fb98dcaeaf5a06a04be (patch)
tree22c2be45b0fe5c029d4c460d8c768f96935a62bc /util
parent209a1bf8cab6413d46399672c9ee402fc5971b54 (diff)
src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode
According to BKDG for AMD Family 16h Models 30h-3Fh Processors SDR50 tuning should be disabled in 0xA8 register. Also fix clock frequency setting in 0xA4 for stepping >= A1 which caused reduced performance of SD cards transfer speed even by half. Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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