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author | Furquan Shaikh <furquan@google.com> | 2019-03-14 15:44:19 -0700 |
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committer | Furquan Shaikh <furquan@google.com> | 2019-03-15 19:52:30 +0000 |
commit | 6e401cf7e6e1ee7ababfebb90def34bb263e3bb4 (patch) | |
tree | f8527a901d82bc71210d3caa8072ec7ef25b59f3 /util | |
parent | 90a96c77a90d7299127e5892cc4806aba37936a6 (diff) |
soc/intel/cannonlake: Fix GEN_PMCON bit checks
CNL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.
BUG=b:128482282
TEST=Verified that prev_sleep_state is reported correctly when booting
from S5.
Change-Id: I75780a004ded8f282ffb3feb0cdc76233ebfd4f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
0 files changed, 0 insertions, 0 deletions