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authorRavi Sarawadi <ravishankar.sarawadi@intel.com>2022-05-07 16:37:09 -0700
committerSubrata Banik <subratabanik@google.com>2022-06-29 05:28:39 +0000
commit91ffac8c04776e1e663c5987ea718522f605a9b4 (patch)
tree255b839904b8aca2206d721f185948c7f27a4865 /util
parentfebd3d756b8ef4c6b6f8b5be9e2558d8cdd5a6ae (diff)
soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Fill required FSP-S UPD to call FSP-S API BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
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