summaryrefslogtreecommitdiff
path: root/util
diff options
context:
space:
mode:
authorNico Huber <nico.h@gmx.de>2017-07-29 01:10:49 +0200
committerNico Huber <nico.h@gmx.de>2017-07-30 00:06:51 +0000
commit2b5c02143152cee95fc189f05cca2243089ab45d (patch)
tree38390ac38a30f8309e30aba4780fa6658b489519 /util
parentf1778ce33366f2005f1ac5e492525012b47d788e (diff)
intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaults
All affected boards did the same USE_NATIVE_RAMINIT distinction or actually selected USE_NATIVE_RAMINIT. Also update autoport. Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20813 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'util')
-rw-r--r--util/autoport/sandybridge.go1
1 files changed, 0 insertions, 1 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index 65042550fd..45d4b0ced4 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -122,7 +122,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
KconfigBool["HAVE_IFD_BIN"] = false
KconfigBool["HAVE_ME_BIN"] = false
- KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000
KconfigInt["MAX_CPUS"] = 8
DSDTIncludes = append(DSDTIncludes, DSDTInclude{