soc/intel/jasperlake: Correct GPIO pad sequence for community pad group

In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)

Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).

Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.

Align pad group as per EDS and pin-ctrl driver in linux kernel.

Reference: DOC#618876 (EDS volume 2)

BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.

Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

0 files changed, 0 insertions, 0 deletions