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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-28 03:12:00 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-28 03:12:00 +0000
commite80ce0a134bc88581db40b02ce250bee5adba3a3 (patch)
treedc52b84fed93361bdf92443ef196764b670f341f /util
parent26f97d2cf9542694f337abf6ce35fe52b23e5108 (diff)
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add to init_fidvid_stage2 some step for my CPU (rev C3) mentioned in BKDG 2.4.2.6 (5) that was missing Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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