Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"

Don't need this additional 2ms delay as PCR read after sideband write
help to fix original hard hang issue.

This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e.

Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>

0 files changed, 0 insertions, 0 deletions