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authorStefan Reinauer <stefan.reinauer@coreboot.org>2020-10-23 01:40:41 +0000
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:56:26 +0000
commit91893ee7857fde783150ea14e376fb63d159aa4d (patch)
tree7abadcbba4bc5436a47f08e056e7cdee0f6452f4 /util
parent28b68ae4fe69bb4bb43b205cb6aa1fd1caa35e32 (diff)
inteltool: initial Hewitt Lake support
Change-Id: Ifed43d058c70f75d88e9f4b2b07527782ebcbac5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util')
-rw-r--r--util/inteltool/inteltool.c2
-rw-r--r--util/inteltool/inteltool.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 91a8b7e025..aadd0fb3c4 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -140,6 +140,8 @@ static const struct {
"10th generation (Comet Lake family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U3,
"10th generation (Comet Lake family) Core Processor (Mobile)" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE,
+ "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index e7d32a3b25..77ad61f410 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -298,6 +298,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */
+#define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */
/* Intel GPUs */